I am facing a serious issue with the Lock Detect signal of the AD9517-1 device. I am not using Analog
Lock Detect or Current Source Lock Detect. Only the normal Digital Lock Detect (DLD).
The SPI communications work ok and I am getting the frequencies I need in the outputs.The issue
that I am trying to solve is why on the LD pin of the device I am receiving a square pulse. The duty
cycle is ~20%. That means the PLL locks for a short time and after unlocks!
My basic settings are present here:
- I am using REF2 as clock source input with a clock 9.216 MHz
- PLL is ON and the VCO frequency is 2359.296 MHz. The VCO Divider is 3.
- The counters have the values: R=1, B=8, A=0, Prescaler (Divide-by-32)
That means in the PFD inputs the compared frequency is 9.216 MHz.
-- For the Lock Detect my settings are : Antibacklash width 2.9ns, High Range
and 5 cycles.
I am using a custom designed board so I don't have the opportunity of changing the loop filter's
characteristics. With ADIsimCLK inserting my boards values it gives a 85.8KHz bandwidth and
60.4 degrees phase margin.
It is important to stabilize the Lock signal since I need to synchronize my peripheral hardware
according to that.
If someone has something to suggest I will be glad.
Thanks a lot in advance.