Struggling to achieve a stable Lock Detect signal with the AD9517-1

Hello,

I am facing a serious issue with the Lock Detect signal of the AD9517-1 device. I am not using Analog

Lock Detect or Current Source Lock Detect. Only the normal Digital Lock Detect (DLD).

The SPI communications work ok and I am getting the frequencies I need in the outputs.The issue

that I am trying to solve is why on the LD pin of the device I am receiving a square pulse. The duty

cycle is ~20%. That means the PLL locks for a short time and after unlocks!

My basic settings are present here:

- I am using REF2 as clock source input with a clock 9.216 MHz

- PLL is ON and the VCO frequency is 2359.296 MHz. The VCO Divider is 3.

- The counters have the values: R=1, B=8, A=0, Prescaler (Divide-by-32)

   That means in the PFD inputs the compared frequency is 9.216 MHz.

-- For the Lock Detect my settings are : Antibacklash width 2.9ns, High Range

    and 5 cycles.

   I am using a custom designed board so I don't have the opportunity of changing the loop filter's

   characteristics. With ADIsimCLK inserting my boards values it gives a 85.8KHz bandwidth and

    60.4 degrees phase margin.

   It is important to stabilize the Lock signal since I need to synchronize my peripheral hardware

    according to that.

   If someone has something to suggest I will be glad.

   Thanks a lot in advance.

   Regards,

   Moysis

  • 0
    •  Analog Employees 
    on Sep 24, 2012 7:29 PM over 8 years ago

    Hello Moysis,

    I can think of four things, three of which are easy, and one takes a little longer:

    1. The LF pin has an internal 32pF of capacitance that SimCLK doesn't account for. Therefore, if SimCLK specifies an final shunt C (assuming a 3rd order loop filter) of 32pF, then you have 64 pF total. This can cause excessive peaking at high loop BWs.

    2. One easy thing to try is different values of the charge pump current to see if the situation improves.

    3. The 220 nF cap to ground from the BYPASS pin to ground is extremely important. Make sure that it's close to the AD9517, and is the correct value.

    4. Can you send me the loop filter that you're using? You can structure your reply by filling in the following fields (going from the CP pin to the LF pin):

    1st shunt C:

    Series R-C (in parallel with 1st shunt C)

    Series R:

    Final shunt C:

    -Paul Kern

  • Hello Paul,

    I am attaching a snapshot from the board's schematic. It contains all the info you requested.

    I tried out different CP currents. My initial setting was 4.8mA. Down to 3mA I didn't saw any difference.

    At 1.2mA the LD is '0'..

    The 220n cap is near the IC in the layout.

    Below I attach also my spi register configuration. The hex value shows the register and the 8 bit

    binary value next to it the register content.

      spi_data(0)  <= ("0000010000","01001111"); -- 0x10

              spi_data(1)  <= ("0000010100","00001000"); -- 0x14

              spi_data(2)  <= ("0000010110","00000110"); -- 0x16

              spi_data(3)  <= ("0000011000","00000110"); -- 0x18

              spi_data(4)  <= ("0000011001","01000000"); -- 0x19

              spi_data(5)  <= ("0000011100","11001100"); -- 0x1C

              spi_data(6)  <= ("0011110000","00011100"); -- 0xF0

              spi_data(7)  <= ("0011110001","00011100"); -- 0xF1

              spi_data(8)  <= ("0011110100","00011100"); -- 0xF4

              spi_data(9)  <= ("0101000010","01001010"); -- 0x142

              spi_data(10) <= ("0110010000","00100010"); -- 0x190

              spi_data(11) <= ("0110010001","00000000"); -- 0x191

              spi_data(12) <= ("0110010110","00100010"); -- 0x196

              spi_data(13) <= ("0110010111","00000000"); -- 0x197

              spi_data(14) <= ("0110011110","00010000"); -- 0x19E

              spi_data(15) <= ("0110100000","00110011"); -- 0x1A0

              spi_data(16) <= ("0111100000","00000001"); -- 0x1E0

              spi_data(17) <= ("0111100001","00000010"); -- 0x1E1

              spi_data(18) <= ("1000110010","00000001"); -- 0X232

    Regards,

    Moysis

  • 0
    •  Analog Employees 
    on Sep 25, 2012 9:38 PM over 8 years ago

    Dear Moysis,

    Try removing C26.

    -Paul Kern

  • Hello Kern,

    I am still facing the same problem after removing C26.

    I can't really see what can be the cause of the issue.

    Here are my latest register configurations.



    "01111100" -- 0x10

    "00001000" -- 0x14

    "00000110" -- 0x16

    "00000110" -- 0x18

    "01000000"-- 0x19

    "11000100" -- 0x1C

    "00011000" -- 0xF0

    "00011000" -- 0xF1

    "00011000"-- 0xF4

    "01001010"-- 0x142

    "00010000" --0x190

    "00000000"-- 0x191

    "00010000"-- 0x196

    "00000000"-- 0x197

    "10111011" -- 0x19E

    "00000000"-- 0x1A0


    "00100000"-- 0x1A1

      "00000001"-- 0x1E0

      "00000010"-- 0x1E1

      "00000001"-- 0X232

    Before I start messing up more with the loop components I would appreciate a look in my

    register settings so I can make sure that I don't have any major mistakes there. After removing C26

    result is the same:

    Frequency division is achieved correctly, but no lock (LD gets high only a while leading to an approximately

    20%DUTY cycle square waveform).

    I almost don't see any difference from before when removing C26.

    Moysis

  • 0
    •  Analog Employees 
    on Oct 4, 2012 6:29 PM over 8 years ago

    Hello Moysis,

    Can you verify that you're doing VCO calibration?  This is done by setting R0x018[0]=1b. VCO calibration will occur during the next IO_UPDATE (R0x232=0x01).

    If you send me an email to paul.kern@analog.com, I can send you a register setup file that is generated by the AD9517 evaluation software. That program has lots of internal checks to ensure that the registers are set up correctly.

    Here's the link to the software:

    http://www.analog.com/static/imported-files/eval_boards/4985179041527AD9516_17_18EvalSetup1.1.0.zip

    Here's a guide to using the software:

    http://www.analog.com/static/imported-files/user_guides/UG-075.pdf

    Here's a tool that will do the frequency planning and loop filter design: (don't worry. The AD9517 and AD9520 are nearly identical in this regard: (Look for the AD9520 config tool and Matlab Runtime installer)

    http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/ad9520-3/products/EVAL-AD9520-3/eb.html