I have a relatively slow clock (nominally 9.38MHz) with appreciable cycle-to-cycle jitter which needs to be removed.
It is important, however, that the input-to-output delay (phase) be consistent across power-up/reset cycles.
(i.e. if the delay at one startup is nominally "n", the delay at the next startup is also nominally "n".
"n" does not need to be zero, it just needs to be the same from run-to-run.)
Is the AD9557 consistent in this way or is there another similar part which would be?