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Questions for your ADN2812

Dear Sir/Madam,

I need your help.

I am just studing with your Data Recovery IC ADN2812.

I would like to set the datarate to 100Mbps.
So I input 12.5MHz clock or 100MHz clock to REFCLK, and confirm the drive, but I cannot catch the good result.

When I set REFCLK to 100Mbps, which should I set CLRLA[7..6] to 10 or 11?

As for the following my set-up, is this no probrem?
  When REFCLK=12.5MHz, CTRLA[7..0]=00001101
  When REFCLK=100MHz, CTRLA[7..0]=10001001

Please give me your good comment.

Thanks Kaos

  • Thank you enash.

    I am still waiting for this reply.


  • Moving this question on ADN2812 to the Clock and Timing Community.

  • Hello Kaos,

    My apologies for the delay. I've asked the appropriate person to review and respond to your question.

    I handle the PLLs.

    -Paul Kern

    Message was edited by: Jeff Keip

  • Hi Dongfeng,

    Great reply!

    I can proceed our job to forward.

    And I can study ADN2812 by your reply.

    Thank you ,Kaos

  • Dear Kaos,

    Yes, an external reference clock can help ADN2812 locking to an input data signal after you have set ADN2812 in "Lock to Reference" mode.

    To do this, you need to write CTRLA[0] = 1.

    In this LTR mode, the ADN2812 locks onto a frequency derived from the reference clock according to:

    Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]               (1)

    You must know exactly what the data rate is and provide a right reference clock and CTRLA setting that satisfies equation 1.

    You need set CTRLA[7:6] properly to inform ADN2812 that which reference clock frequency you have used with this ADN2812.

    Table 11 of ADN2812 datasheet shows the recommended settings:

    Table 11. CTRLA[7:6] Settings


    Range (MHz)


    12.3 to 25


    25 to 50


    50 to 100


    100 to 200

    In your case, if select a clock source of 12.5MHz, you need to set CTRLA[7:6] = 0x00b.

    From the equation 1, 2CTRLA[5:2] = 100Mbps / ( 12.5MHz/20 ) = 8, and CTRLA[5:2] = 0x0011b.

    In this way, using ADN2812 and a 12.5MHz clock to lock to a 100Mbps input data,

    you need to write CTRLA[7:0] =0x00001101b or CTRLA[7:0] = 0x0DH.

    If select a clock source frequency of 100MHz, you may either set CTRLA[7:6] = 10 or CTRLA[7:6] = 11.

    Following the same process discussed above, you could write

    either    CTRLA[7:0] = 0x10001001b; CTRLA[7:0] = 0x89H, or

                CTRLA[7:0] = 0x11001101b; CTRLA[7:0] = 0xCDH.

    Hope these are useful to your ADN2812 application. Thank you again for being interested in ADN2812.

    Best Regards,

    Dongfeng Zhao

  • Hi, Dongfeng

    Today, I could be worked ADN2812 well.

    Thank you for your great support!