Thank FormerMember for providing the firmware file to me very much.
Using this firmware, test signal on the evaluation software can basically normal display
However, the output of the clock can not be locked.
OUT0 output spectrum of the 100MHz signal were shown as in the following two figures:
20MHz reference source is the phase noise is displayed as in the following two shown:
I do not know what is the reason of the loop can not be locked, and want to be able to help me analyze.
Can you provide the loop filter parameters of the ad9518 schematic.pdf in ADIsimCLK software simulation files for me ?
I want to know the relevant parameters such as the loop bandwidth etc.
Otherwise it is impossible to modify the parameters of the loop filter make loop circuit lock.
I debug the AD9518-1 and AD9518-0 two devices, and the result is the same.
Hope to get your help again。
I want to know what you willing to provide the debug software AD9516_17_18 Evaluation Software source code to me,
I hope to be able to better understand the working process of this device.