Synchronizing multiple AD9517-1

I am using the AD9517 on two boards, and i am trying to synchronize all outputs such that the phase/timing between outputs on both board are repeatable at every power-up or reset cycle.

I have made all the necessary provisions:

1. External 10MHz reference to both AD9517 to be able to lock to the same reference.I have the external ref clock split into two and provided to each board.

2. AD9517 in PLL mode with an external VCO generating 1GHz clock output.

3. An FPGA on each board provides SYNC signal after the AD9517 indicates that lock is achieved. So i do not have 1 SYNC source that is split to the two AD9517.

I am having issues with getting the divided clock outputs on the two boards (250MHz clock, divided by 4 version of 1GHz) to come up with constant phase relationship at every power-up. At every power-up the FPGA on each board performs SPI Programming ==> LD status Check ==> SYNC ==> Done.

Is there any document that describes the desired sync procedure for multiple AD9517 ? Or, is there any problem with the setup i have described ?

Many thanks,

AB

  • 0
    •  Analog Employees 
    on Jan 27, 2014 11:24 PM over 7 years ago

    Dear Arvabj,

    The AD9517 doesn't have a zero delay mode, but the AD9520 and AD9522 (which AD9517's cousins) have this feature.

    The way to achieve zero delay on the AD9517 is to provide a low-to-high pulse on the SYNCb pins of both parts that is synchronous to the ref input clock. Hopefully, your FPGAs can do this.

    You'll need to experiment with the exact placement of the SYNCb edge relative to the ref edge to stay away from the one cycle of uncertainty (relative to the AD9517 Channel divider input clock).

    -Paul Kern

  • Thanks Paul,

    I am considering using AD9520 for another application due to the zero delay. Can i synchronize multiple AD9520 devices on different boards (with common ref clock and syncb signals) when using the internal VCO of the AD9520 ? Please advice.

    thanks,

    Arvind

  • 0
    •  Analog Employees 
    on Feb 12, 2014 11:59 PM over 7 years ago

    Hi Arvabj,

    > I am considering using AD9520 for another application due to the zero delay. Can i synchronize multiple AD9520 devices on different boards (with common ref clock and syncb signals) when using the internal VCO of the AD9520 ? Please advice.

    Yes. If both are set up in zero delay mode, then both will have a known phase relationship to the input. Most of you variation between the two will be related to temp and voltage differences between the two.

    -Paul Kern

  • Hi Arvind, Paul,

    I am re-spinning a board which used a AD9518-3 and am considering moving to the AD9520 for the same reason Arvind mentioned- I need to synchronize multiple boards each using its own PLL (an AD9520).  Arvind- did you have success/insight using this approach?  Did you experiment with timing of the syncb signal directly from the FPGA, or, use some external means (like a D-flip-flop) to provide the synchronization.  My main concern is the "uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9520" and if that can be mitigated repeatedly using this approach.

    Thanks in advance,

    Dan  

  • 0
    •  Analog Employees 
    on May 28, 2014 12:21 AM over 6 years ago

    Hi Dan,

    > My main concern is the "uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9520" and if that can be mitigated repeatedly using this approach.

    I should clarify this statement. If you vary the SYNCB edge continuously with respect to the ref input clock, you're guaranteed at some point to have one cycle (as measured at the input to the AD9518 channel divider) uncertainty. However, if you avoid the region where it's uncertain which edge will be chosen, this uncertainty will not exist.

    The designer should have the ability to adjust (even in a coarse manner) the placement of the SYNCB pulse with respect to REFIN in order to guarantee there's no uncertainty.

    -Paul Kern