AD9559 : 0.1Hz loop bandwidth

Hello,

I have a question about loop bandwidth of AD9559 device.

In datasheet, AD9559 supports 0.1hz to 2khz loop bandwidth.

The DPLL is working well in the default configuration (50hz loop bandwidth)

But when we set the loop bandwidth to 0.1hz, the DPLL does not phase locked (frequency is locked).

Our design use 12.8Mhz TCXO, but 12.8MHz OCXO also cannot phase locked.

The frequency / phase lock threshold is 1000ps.

Please let me know the check points.

 

Thanks & Best regards,

MK

  • 0
    •  Analog Employees 
    on Jan 28, 2014 12:09 AM

    Hi mkkwak,

    First, the sysclk doubler should be disabled when using a low-frequency system clock.

    Next, have a look at the system clock waveform. The voltage divider recommendations in the datasheet are a good starting point, but the best settings depend on the CMOS driver itself. Ideally, the waveform should be 1Vpp square wave with approximately 50% duty cycle. We even added a place for a pull-up resistor (R211) so that the OCXO CMOS driver can both sink and source current.

    Once you have a good  SYSCLK waveform, try gradually lower and lower loop BWs to see how far away you are.

    The required system clock stability goes up with the inverse square of bandwidth, so not every TCXO (or OCXO) will be good enough.

    -Paul Kern

  • Hi Paul,

    Thank you for reply.

    I've measured the system clock waveform, the voltage is 0.98Vpp square wave but the duty cycle is 46/54%.

    Does this duty cycle affect the 0.1hz loop bandwidth ?

    I read the TCXO vendor datasheet (Rakon, Vectron), and the duty cycle is normally 45/55%.

    Could you let me know the recommended TCXO (or OCXO) part ?

    And I have tested as your guide.

    First disable doubler, and trying gradually lower loop BW.

    The DPLL can phase lock about 4Hz loop bandwidth.

    Thanks and best regards.

    MK

  • 0
    •  Analog Employees 
    on Feb 4, 2014 2:54 AM

    Dear Mkkwak,

    > I've measured the system clock waveform, the voltage is 0.98Vpp

    > square wave but the duty cycle is 46/54%.

    > Does this duty cycle affect the 0.1hz loop bandwidth ?

    Not if the system clock doubler is disabled. If it's enabled, there's a very good chance you'll never get system clock stable, and even if you do, the duty cycle asymmetry will make the system clock less stable.

    > I read the TCXO vendor datasheet (Rakon, Vectron), and the duty cycle is normally 45/55%.

    > Could you let me know the recommended TCXO (or OCXO) part ?

    Any high quality TCXO, like a Vectron TX-700. The higher the frequency, the better.

    > And I have tested as your guide. First disable doubler, and trying gradually lower loop BW.

    > The DPLL can phase lock about 4Hz loop bandwidth.

    The topic of "Phase Lock" is always an interesting one, as there is no universally accepted definition for it. The default phase lock threshold settings in the part are just a somewhat arbitrary setting, and it's up to the user to decide the correct threshold for their application. We've seen cases where the lock detect is chattering but the user's system is still passing error-free traffic.

    In light of that, you might try increasing the phase lock threshold. It's not uncommon to do that when the loop BW gets really low.

    -Paul Kern

  • Hi Paul,

    Thank you for your advice.

    I've tested increasing the phase lock threshold, and the DPLL can phase lock about 200ns phase lock threshold.

    We succeed in G.8262 wander test, but I'm not sure this value is reasonable threshold.

    I have one more question about base loop filter selection (normal phase margin and high phase margin).

    When I set the high phase margin, the phase lock time is about 20 minutes.

    In normal phase margin, the phase lock time is about 10 seconds.

    Could you explain this lock time?

    Thanks and best regards.

    MK

  • 0
    •  Analog Employees 
    on Feb 10, 2014 7:33 PM

    Hi Mkkwak,

    Thank you for your advice.

    > I've tested increasing the phase lock threshold, and the DPLL can phase lock about

    > 200ns phase lock threshold. We succeed in G.8262 wander test, but I'm not sure this

    > value is reasonable threshold.

    How to set the ideal lock threshold is an interesting question. Another good question is why our (somewhat) arbitrarily chosen thresholds are any more meaningful. It seems to me that the only meaningful way to set the threshold is such that your system doesn't drop traffic or fail any tests when it's locked.

    > I have one more question about base loop filter selection (normal phase margin and high phase margin).

    > When I set the high phase margin, the phase lock time is about 20 minutes.

    > In normal phase margin, the phase lock time is about 10 seconds.

    > Could you explain this lock time?

    Absolutely. The high phase margin case is an extremely over-damped loop. One thing you can do is use normal phase margin for acquisition, and high PM after lock.

    -Paul

    Thanks and best regards.

    MK