I have a question about loop bandwidth of AD9559 device.
In datasheet, AD9559 supports 0.1hz to 2khz loop bandwidth.
The DPLL is working well in the default configuration (50hz loop bandwidth)
But when we set the loop bandwidth to 0.1hz, the DPLL does not phase locked (frequency is locked).
Our design use 12.8Mhz TCXO, but 12.8MHz OCXO also cannot phase locked.
The frequency / phase lock threshold is 1000ps.
Please let me know the check points.
Thanks & Best regards,