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AD9511 with CVHD-950 VCXO

We're designig a product that requires both a very good frequency stability and a very low phase noise and jitter as we need to clock a 14 bit 170Msps ADC (an AD9643), an AD9707 DAC and get a reference for an ADF4351 synthesizer.

We're going to use two crystal oscillators, a ultra stable reference (in the low 100's of ppb range) and a ultra low phase noise VCXO and "combine" them with a PLL. We thought about the CVHD-950 series from crystek for VCXO. According to ADIsimCLK simulations it is a little bit overkill for our application as we're sampling at 1st nyquist zone but it's a very cheap part compared to other products that would barely meet performance requirements and cost about the same. As for the pll/distribution chip we found that AD9511 meets our requirements very well and it has the exact number and type of outputs we need. However it seems that the CVHD-950 can't directly interface to AD9511's CLK2 input as it has 3.3V CMOS output and the AD9511's max input swing is only 2 Vpp and should also be AC-coupled.

Could you recommend a simple interface circuit for this case? The VCXO will run at 122,88 MHz

  • Hi David,

    The easiest way to interface these components is to create a resistor divider at the output of the VCXO to lower the swing of the CVHD-950.  The unused input can be ac-coupled to ground.  I have copied an image from the AD9525 datasheet which shows a similar configuration.

    Regards,
    Kyle

  • I was thinking about using a resistor divider but wouldn't that create a low pass filter with the input capacitance of the chip?

  • Hi David,


    Yes this will create a low pass but you can select the resistance values such that the bandwidth is much higher than your VCXO frequency.  You will attenuate some harmonics and decrease the slew of your clock signal but, we have seen that performance is preserved with minor degradation of the VCXO slew rate.  Using the 100k resistors shown in my initial reply will set the cutoff frequency too low for a 122.88MHz VCXO.


    I did a few simulations by using 300ohm and 150ohm resistors in the voltage divider and used typical output capacitance values from the CVHD-950 datasheet and our typical CLKIN receiver capacitance.  These are more appropriate values.

    Regards,
    Kyle

  • Thank you very much, I had already done my own simulations and came to values very similar to yours but I was still a bit concerned about slew rate performance degradation.

    Just to be sure, can I apply the same input scheme to the reference input? Any concerns about slew rate there?

  • Hi David,


    Yes, the same scheme can be applied.  The receivers should be similar.  I don't have a hard specification to quote for a minimum input slew rate but I don't foresee any issues with slightly degraded typical CMOS slew rates.

    Regards,
    Kyle