I'm using an AD9522-3. The reference clock is 100 MHz. The VCO will operate at 2000 MHz. OUT0 will run at 100 MHz, and be fed back to the AD9522 for zero delay alignment.
In ADIsimCLK, I select the AD9522-3 and then check "Use Zero Delay". I select OUT0 for feedback, a VCO divider of 2, and an Arm divider of 10. I enter a PLL/VCO frequency of 2.00 GHz, and a Phase Detector Frequency of 100.0 MHz. When I click "Next", ADIsimCLK pops up an "Error" window saying that the AD9522-3 is incompatible with these frequencies, and that no valid prescaler option could be found.
I believe this is happening because ADIsimCLK is assuming that the VCO is being fed to the prescaler/N divider instead of CLK0. For my case, where the reference clock is equal to the feedback clock, I think the R and N dividers should both be set to 1, and 100 MHz is within spec for both the PFD and the prescaler. Can anyone confirm this bug or suggest a fix/workaround?
I am seeing the same issue. This is a valid configuration. An easy work around is to use the AD9522-4 model and instead of a total feedback of 20, use a feedback of 16.
The model for the AD9522-4 will be an accurate representation of AD9522-3 phase noise but the loop dynamics will be calculated based on a feedback divider of 16. If you need to configure an AD9522-3 evaluation board with a total feedback of 20, you can simply use the loop filter from the AD9522-4 ADIsimCLK file and scale the charge pump current up by 25%. The basic equation to find the loop bandwidth of a PLL is given below, which shows that you can scale the charge pump current to offset the scaled N.