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AD9518-3, Phase noise due to two Ref clocks.

Thread Summary

The user is experiencing phase noise sidebands on a 1GHz output from the AD9518-3 when using two single-ended reference clocks (REF1 and REF2) with a small frequency difference. The final answer suggests that bond-wire coupling is the cause and recommends using series resistors or an external 2:1 mux to reduce the signal levels and minimize coupling. Proper PCB routing and impedance matching are also emphasized as critical for reducing phase noise.
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Hi,

I'm using the AD9518-3 to generate a 1GHz clock for my DDS.

I provide REF1 in the form of a 10MHz TCXO, single ended.

The AD9518-3 produces beautiful 1GHz outputs. The phase noise is better than my portable HP spectrum

analyzer can measure. Nice! That's great! For this test, REF1 is the only clock connected.

REF2 will be an additional, external clock for this subsystem. When I keep REF1 connected

and then connect REF2, I see phase noise sidebands on my 1GHz signal at twice

the difference frequency of REF1 and REF2.

E.g., REF1 = 10MHz, REF2 = 9.997 MHz, I see sidebands on the 1GHz output

at 6kHz, 12kHz, 18kHz,etc. The first sideband is -30dBc! Wow! Not good!

Note that I see the same effect when I lock to REF2, rather than REF1.

Can't this chip run with 2 single-ended clocks connected without there being cross-talk phase noise?

Thanks,

David

Parents
  • Hi David,

    > I'll follow your lead of an external mux further, by completely disabling the external clock buffer

    on the unused REF inputs. This will stop the CMOS much signal farther away from the AD9518,

    probably a couple of cm away.

    This is an "either-or" thing. The best approach is to squelch the unused SE CMOS input. The next best approach is to use a dumb 2:1 mux, and come differentially into our part. The risk in using a mux is that you may be disappointed by that mux's ability to isolate two 3.3V CMOS inputs.

    > I have to re-spin the board to add protection against cable discharge events (such voodoo!) anyway.

    Yep. I dealt with that in Ethernet PHY land quite a bit.

    > The tests I performed to see this effect are a bit strange, I admit. Why would there ever be a need for

    > inputs of REF1 and REF2 differing by a few parts in 10^4? A few ppm is more realistic.

    Correct. You'll see a lot of parts from different vendors not cope well with with two 3.3V CMOS ref inputs that close in frequency unless you go with more exotic PLLs (which we also have.)

    Overall, the AD9518 is a super part, but single-ended 3.3V CMOS reference input isolation was (obviously) not a primary objective during design.

    -Paul Kern

Reply
  • Hi David,

    > I'll follow your lead of an external mux further, by completely disabling the external clock buffer

    on the unused REF inputs. This will stop the CMOS much signal farther away from the AD9518,

    probably a couple of cm away.

    This is an "either-or" thing. The best approach is to squelch the unused SE CMOS input. The next best approach is to use a dumb 2:1 mux, and come differentially into our part. The risk in using a mux is that you may be disappointed by that mux's ability to isolate two 3.3V CMOS inputs.

    > I have to re-spin the board to add protection against cable discharge events (such voodoo!) anyway.

    Yep. I dealt with that in Ethernet PHY land quite a bit.

    > The tests I performed to see this effect are a bit strange, I admit. Why would there ever be a need for

    > inputs of REF1 and REF2 differing by a few parts in 10^4? A few ppm is more realistic.

    Correct. You'll see a lot of parts from different vendors not cope well with with two 3.3V CMOS ref inputs that close in frequency unless you go with more exotic PLLs (which we also have.)

    Overall, the AD9518 is a super part, but single-ended 3.3V CMOS reference input isolation was (obviously) not a primary objective during design.

    -Paul Kern

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