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AD9518-3 Recommended for New Designs
The AD9518-31 The AD9518-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO...
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AD9518-3 on Analog.com

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AD9518-3, Phase noise due to two Ref clocks.

		
	
				

			

									
					    DavidLee
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 27, 2015 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is experiencing phase noise sidebands on a 1GHz output from the AD9518-3 when using two single-ended reference clocks (REF1 and REF2) with a small frequency difference. The final answer suggests that bond-wire coupling is the cause and recommends using series resistors or an external 2:1 mux to reduce the signal levels and minimize coupling. Proper PCB routing and impedance matching are also emphasized as critical for reducing phase noise.
                        	    
    
                
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    Hi,
    
 
    I'm using the AD9518-3 to generate a 1GHz clock for my DDS.
    
 
    I provide REF1 in the form of a 10MHz TCXO, single ended.
    
 
    The AD9518-3 produces beautiful 1GHz outputs. The phase noise is better than my portable HP spectrum
    
 
    analyzer can measure. Nice! That's great! For this test, REF1 is the only clock connected.
    
 
    REF2 will be an additional, external clock for this subsystem. When I keep REF1 connected
    
 
    and then connect REF2, I see phase noise sidebands on my 1GHz signal at twice
    
 
    the difference frequency of REF1 and REF2.
    
 
    E.g., REF1 = 10MHz, REF2 = 9.997 MHz, I see sidebands on the 1GHz output
    
 
    at 6kHz, 12kHz, 18kHz,etc. The first sideband is -30dBc! Wow! Not good!
    
 
    Note that I see the same effect when I lock to REF2, rather than REF1.
    
 
    Can't this chip run with 2 single-ended clocks connected without there being cross-talk phase noise?
    
 
    Thanks,
    
 
    David
    
			
    
			
									
		                             
                        

    
    
                                            
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2015 8:55 PM
            
            
						
			            		
      
		
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      Hi David,
      
 
      > Are you saying that applying 2 reference clocks to the AD9518
      
 
      > produces no excess phase noise on a "perfect" PCB?
      
 
      No. Of course not. The "perfect" PCB would have all differential clocks or tons of room to isolate the SE clocks. For the AD9518, ideally, we would have two differential inputs, but we didn't have enough pins, and the target market for the part was primarily interested in having only one differential input. Unfortunately, these are the trade-offs we had to make with the part.
      
 
      > The clocks are widely separated until they meet at the chip. Note that REF1 and REF2 are *adjacent* on the chip.
      
 
      > I have tried turning off the unused reference input. I still see excess phase noise.
      
 
      You're seeing bond-wire coupling.
      
 
      > You suggested reducing the signal levels. These are CMOS logic levels. How should they be reduced?
      
 
      Do you have any place for series resistors?
      
 
      You could put a "dumb" 2:1 mux in front of our part, but to be honest, I've seen cases where even their performance is underwhelming.
      
 
      -Paul Kern
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2015 8:55 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hi David,
      
 
      > Are you saying that applying 2 reference clocks to the AD9518
      
 
      > produces no excess phase noise on a "perfect" PCB?
      
 
      No. Of course not. The "perfect" PCB would have all differential clocks or tons of room to isolate the SE clocks. For the AD9518, ideally, we would have two differential inputs, but we didn't have enough pins, and the target market for the part was primarily interested in having only one differential input. Unfortunately, these are the trade-offs we had to make with the part.
      
 
      > The clocks are widely separated until they meet at the chip. Note that REF1 and REF2 are *adjacent* on the chip.
      
 
      > I have tried turning off the unused reference input. I still see excess phase noise.
      
 
      You're seeing bond-wire coupling.
      
 
      > You suggested reducing the signal levels. These are CMOS logic levels. How should they be reduced?
      
 
      Do you have any place for series resistors?
      
 
      You could put a "dumb" 2:1 mux in front of our part, but to be honest, I've seen cases where even their performance is underwhelming.
      
 
      -Paul Kern
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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