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AD9518-3 Recommended for New Designs
The AD9518-31 The AD9518-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO...
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AD9518-3 on Analog.com

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AD9518-3, Phase noise due to two Ref clocks.

		
	
				

			

									
					    DavidLee
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 27, 2015 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user is experiencing phase noise sidebands on a 1GHz output from the AD9518-3 when using two single-ended reference clocks (REF1 and REF2) with a small frequency difference. The final answer suggests that bond-wire coupling is the cause and recommends using series resistors or an external 2:1 mux to reduce the signal levels and minimize coupling. Proper PCB routing and impedance matching are also emphasized as critical for reducing phase noise.
                        	    
    
                
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    Hi,
    
 
    I'm using the AD9518-3 to generate a 1GHz clock for my DDS.
    
 
    I provide REF1 in the form of a 10MHz TCXO, single ended.
    
 
    The AD9518-3 produces beautiful 1GHz outputs. The phase noise is better than my portable HP spectrum
    
 
    analyzer can measure. Nice! That's great! For this test, REF1 is the only clock connected.
    
 
    REF2 will be an additional, external clock for this subsystem. When I keep REF1 connected
    
 
    and then connect REF2, I see phase noise sidebands on my 1GHz signal at twice
    
 
    the difference frequency of REF1 and REF2.
    
 
    E.g., REF1 = 10MHz, REF2 = 9.997 MHz, I see sidebands on the 1GHz output
    
 
    at 6kHz, 12kHz, 18kHz,etc. The first sideband is -30dBc! Wow! Not good!
    
 
    Note that I see the same effect when I lock to REF2, rather than REF1.
    
 
    Can't this chip run with 2 single-ended clocks connected without there being cross-talk phase noise?
    
 
    Thanks,
    
 
    David
    
			
    
			
									
		                             
                        

    
    
                                            
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                 Clock Generation and Distribution
                
                                                    
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                 ad9518-3
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2015 8:24 PM
            
            
						
			            		
      
		
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      Hi David,
      
 
      Keeping adjacent 3.3V CMOS single-ended inputs from coupling is always challenging with any part, and we have had customers who have been happy with the AD9518 performance when driven by two single-ended inputs. 
      
 
      The keys to getting this are:
      
 
      1. Ensuring that the SE clocks are routed for maximum spacing on your board.
      
 
      2. Ensuring that proper impedance matching techniques are followed.
      
 
      You can try reducing the input amplitude, or turning off the unused input receiver. However, the latter fix won't help if there is board-level coupling.
      
 
      The best way to minimize coupling and maximize performance is to reduce the amplitude while maintaining the input slew rate.
      
 
      I hope this helps.
      
 
      -Paul Kern
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 27, 2015 8:24 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hi David,
      
 
      Keeping adjacent 3.3V CMOS single-ended inputs from coupling is always challenging with any part, and we have had customers who have been happy with the AD9518 performance when driven by two single-ended inputs. 
      
 
      The keys to getting this are:
      
 
      1. Ensuring that the SE clocks are routed for maximum spacing on your board.
      
 
      2. Ensuring that proper impedance matching techniques are followed.
      
 
      You can try reducing the input amplitude, or turning off the unused input receiver. However, the latter fix won't help if there is board-level coupling.
      
 
      The best way to minimize coupling and maximize performance is to reduce the amplitude while maintaining the input slew rate.
      
 
      I hope this helps.
      
 
      -Paul Kern
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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