AD9518-3, Phase noise due to two Ref clocks.

Hi David,

Keeping adjacent 3.3V CMOS single-ended inputs from coupling is always challenging with any part, and we have had customers who have been happy with the AD9518 performance when driven by two single-ended inputs.

The keys to getting this are:

1. Ensuring that the SE clocks are routed for maximum spacing on your board.

2. Ensuring that proper impedance matching techniques are followed.

You can try reducing the input amplitude, or turning off the unused input receiver. However, the latter fix won't help if there is board-level coupling.

The best way to minimize coupling and maximize performance is to reduce the amplitude while maintaining the input slew rate.

I hope this helps.

-Paul Kern

Hi Paul,

Thanks for the reply.

Are you saying that applying 2 reference clocks to the AD9518 produces no excess phase noise

on a "perfect" PCB?

The clocks are widely separated until they meet at the chip. Note that REF1 and REF2 are *adjacent* on the chip.

You suggested reducing the signal levels. These are CMOS logic levels. How should they be reduced?

I have tried turning off the unused reference input. I still see excess phase noise.

Cheers,

David

Hi David,

> Are you saying that applying 2 reference clocks to the AD9518

> produces no excess phase noise on a "perfect" PCB?

No. Of course not. The "perfect" PCB would have all differential clocks or tons of room to isolate the SE clocks. For the AD9518, ideally, we would have two differential inputs, but we didn't have enough pins, and the target market for the part was primarily interested in having only one differential input. Unfortunately, these are the trade-offs we had to make with the part.

> The clocks are widely separated until they meet at the chip. Note that REF1 and REF2 are *adjacent* on the chip.

> I have tried turning off the unused reference input. I still see excess phase noise.

You're seeing bond-wire coupling.

> You suggested reducing the signal levels. These are CMOS logic levels. How should they be reduced?

Do you have any place for series resistors?

You could put a "dumb" 2:1 mux in front of our part, but to be honest, I've seen cases where even their performance is underwhelming.

-Paul Kern

Hey Paul,

Thanks!

I'll follow your lead of an external mux further, by completely disabling the external clock buffer

on the unused REF inputs. This will stop the CMOS much signal farther away from the AD9518,

probably a couple of cm away.

I have to re-spin the board to add protection against cable discharge events (such voodoo!) anyway.

The tests I performed to see this effect are a bit strange, I admit. Why would there ever be a need for

inputs of REF1 and REF2 differing by a few parts in 10^4? A few ppm is more realistic.

Thanks for the help,

David

Hi David,

> I'll follow your lead of an external mux further, by completely disabling the external clock buffer

on the unused REF inputs. This will stop the CMOS much signal farther away from the AD9518,

probably a couple of cm away.

This is an "either-or" thing. The best approach is to squelch the unused SE CMOS input. The next best approach is to use a dumb 2:1 mux, and come differentially into our part. The risk in using a mux is that you may be disappointed by that mux's ability to isolate two 3.3V CMOS inputs.

> I have to re-spin the board to add protection against cable discharge events (such voodoo!) anyway.

Yep. I dealt with that in Ethernet PHY land quite a bit.

> The tests I performed to see this effect are a bit strange, I admit. Why would there ever be a need for

> inputs of REF1 and REF2 differing by a few parts in 10^4? A few ppm is more realistic.

Correct. You'll see a lot of parts from different vendors not cope well with with two 3.3V CMOS ref inputs that close in frequency unless you go with more exotic PLLs (which we also have.)

Overall, the AD9518 is a super part, but single-ended 3.3V CMOS reference input isolation was (obviously) not a primary objective during design.

-Paul Kern

pkern wrote:

> I have to re-spin the board to add protection against cable discharge events (such voodoo!) anyway.

Yep. I dealt with that in Ethernet PHY land quite a bit.

 

How cool would it be to have a cable termination named after you!? (e.g., the Bob Smith termination).