AD9522-1 internal VCO problem

Hi,

I designed a PCB that includes an AD9522-1 that I intend to use for clock distribution. The supporting circuitry for the AD9522-1 is basically a copy of the AD9522/PCBZ Evaluation Board (which I also use to program the AD9522-1 in my design by means of the AD9522 Evaluation Software).

I program the AD9522-1 in order to output several clks of 200 MHz locked to a 10 MHz input signal. I use the following configuration:

  • Operational Mode: Internal VCO and CLK Distribution
  • PLL Mode: Norm Op
  • REF1: 10 MHz input
  • R Divider =1
  • N Divider=240
  • VCO Divider=2
  • Channel Divider=6

This configuration works fine when using the Eval Board. However, I am unable to get an clk output when using my design. At the most, I get a high level signal when I program an output channel in CMOS format. Using the STATUS pin, I have verified the following:

  1. The R Divider Output is correct.
  2. The N Divider Output is always low.

Even though the absolute absence of an output signal suggests me that it is not a problem of the external loop nor the charge pump current, I have tried changing these parameters with no success. As for a chip or soldering failure, I get the same results in three different PCBs.

My feeling is that I am missing something quite basic, any suggestions?

Thank you very much.

  • 0
    •  Analog Employees 
    on Mar 16, 2015 7:37 PM

    Hi Daniel,

    If you copied the AD9522-1 eval board loop filter, you'll need to increase the R and N dividers such that the max PFD frequency is about 1 to 2 MHz because the eval board loop filter is optimized for lower loop bandwidths. I recommend setting the R divider to 10, and the N divider to 2400, and setting Icp=0.6mA.

    In general, there are seven basic steps to bringing up the AD9522:

    1. Configure all of the dividers and output drivers.(Leave R0x018[0]=0b at this point.)

    2. Power up the PLL. (R0x010=0x0C to 0x7C, depending on the desired charge pump current.)

    3. Turn on the input receiver.

    4. Change the mux to select the internal VCO instead of CLK input (Located in Reg 0x1E1[1]).

    5. Make all of the register values active by writing R0x232=0x01. (This is also called an "IO_UPDATE.")

    5. Set the VCO calibration bit (R0x018[0]=1b)

    7. Issue another IO_UPDATE, ensuring that the input reference signal is present before doing this.

    See this link for more information about programming the AD9522:

    http://www.analog.com/media/en/technical-documentation/user-guides/UG-077.pdf

    -Paul Kern

  • Hi Paul,

    Thank very much for your answer. I tried changing the R and N dividers without any success. As I said before, I don´t think the main problem is loop related since I use the same configuration that works fine when I use the Eval Board. Furthermore, in think that if this was the problem, I would at least see an unlocked output (in contrast to the 0V LVDS signal or +3.3V CMOS outputs I now get).

    In my opinion, there seems to be a problem with the VCO. ¿Is there a simple way to check if the VCO is working? ¿Can I apply a DC voltage directly to the LF pin?

    Best regards.

  • 0
    •  Analog Employees 
    on Mar 18, 2015 10:12 PM

    Hi Daniel,

    Is the PLL locked?

    -Paul

  • Hi Paul,

    No, according to the LD pin output (DLD option) the PLL is not locked.

    Regards.

    Daniel

  • 0
    •  Analog Employees 
    on Apr 2, 2015 9:42 PM

    Hi Daniel,

    Please email me (paul.kern@analog.com) your schematic and register setting (.STP) file.

    -Paul