AD9517-0
Recommended for New Designs
The AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip...
Datasheet
AD9517-0 on Analog.com
Hello everyone:
I am using one AD9517-0 LVPECL output to drive a fanout buffer to convert the signal to two LDVS signals.
In the AD9517-0 datasheet I can see this figure to interface LVPECL stages:
On the other hand, in the datasheet of the fanout buffer, I can see this other configuration:
My dessign follows the AD recomendation (first schematic) and incorporates R1 to R4 of the second schematic.
Question: Should I keep the 100 Ohn resistor at the imput of the receiver (as proposed in the AD schematic)?
Thanks in advance
Regards
GuiX
Dear Paul and Kyle,
Thank you very much for your advise.
1.- Please, let me know if the next schematic is correct (the 100 Ohm resistor is not mounted):
2.- Paul suggest to use the LVPECL output on the AD9517-0 in a LVDS compatible mode. What is the maximum frequency for this configuration? The AD9517-0 LVDS outputs maximum frequency is 800 MHz.
Thank you in advance
Regards
GuiX
Dear Paul and Kyle,
Thank you very much for your advise.
1.- Please, let me know if the next schematic is correct (the 100 Ohm resistor is not mounted):
2.- Paul suggest to use the LVPECL output on the AD9517-0 in a LVDS compatible mode. What is the maximum frequency for this configuration? The AD9517-0 LVDS outputs maximum frequency is 800 MHz.
Thank you in advance
Regards
GuiX
