AD9517-0
Recommended for New Designs
The AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip...
Datasheet
AD9517-0 on Analog.com
Hello everyone:
I am using one AD9517-0 LVPECL output to drive a fanout buffer to convert the signal to two LDVS signals.
In the AD9517-0 datasheet I can see this figure to interface LVPECL stages:
On the other hand, in the datasheet of the fanout buffer, I can see this other configuration:
My dessign follows the AD recomendation (first schematic) and incorporates R1 to R4 of the second schematic.
Question: Should I keep the 100 Ohn resistor at the imput of the receiver (as proposed in the AD schematic)?
Thanks in advance
Regards
GuiX
Hi GuiX,
Our datasheet figure with the 100 ohm differential termination assumes that the LVPECL receiver is self biased. The clock buffer figure (2D) is biasing the receiver to a ~2V common mode using an external 3.3V supply and resistor divider and is also setting the input impedance to ~50 ohms (84||125) to match each trace to the receiver.
The 100ohm differential resistor is not needed when using the clock buffer termination diagram. Please let me know if I can help further.
Regards,
Kyle
Hi GuiX,
Our datasheet figure with the 100 ohm differential termination assumes that the LVPECL receiver is self biased. The clock buffer figure (2D) is biasing the receiver to a ~2V common mode using an external 3.3V supply and resistor divider and is also setting the input impedance to ~50 ohms (84||125) to match each trace to the receiver.
The 100ohm differential resistor is not needed when using the clock buffer termination diagram. Please let me know if I can help further.
Regards,
Kyle