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AD9517-0 Recommended for New Designs
The AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip...
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AD9517-0 on Analog.com

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AD9517 LVPECL output interface to a fanout buffer

		
	
				

			

									
					    GuiX
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Mar 23, 2015 
				
			
			
		
    
		
		                    	    
    
        	    
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                The user asked if a 100 ohm resistor should be kept at the input of an LVDS receiver when using an AD9517-0 LVPECL output to drive it. The final answer from the support engineer indicates that the 100 ohm resistor is not needed and would halve the signal amplitude. The support engineer also noted that the maximum frequency for LVPECL to LVDS conversion is 1.6 GHz, as this is the highest frequency at which the amplitude is sufficient for most LVPECL receivers to function properly.
                        	    
    
                
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    Hello everyone:
    
 
    I am using one AD9517-0 LVPECL output to drive a fanout buffer to convert the signal to two LDVS signals.
    
 
    In the AD9517-0 datasheet I can see this figure to interface LVPECL stages:
    
 
    
 
    On the other hand, in the datasheet of the fanout buffer, I can see this other configuration:
    
 
    
 
    My dessign follows the AD recomendation (first schematic) and incorporates R1 to R4 of the second schematic.
    
 
    Question: Should I keep the 100 Ohn resistor at the imput of the receiver (as proposed in the AD schematic)?
    
 
    Thanks in advance
    
 
    Regards
    
 
    GuiX
    
			
    
			
									
		                             
                        

    
    
                                            
                 Clock Generation Devices
                
                                                    
                 Clock Generation and Distribution
                
                                                    
                 AD9517-0
                
                                                    
                 Clocks & Timers
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Mar 23, 2015 6:25 PM
            
            
						
			            		
      
		
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      Hi GuiX,
      
 
      Our datasheet figure with the 100 ohm differential termination assumes that the LVPECL receiver is self biased.  The clock buffer figure (2D) is biasing the receiver to a ~2V common mode using an external 3.3V supply and resistor divider and is also setting the input impedance to ~50 ohms (84||125) to match each trace to the receiver.
      
 
      The 100ohm differential resistor is not needed when using the clock buffer termination diagram.  Please let me know if I can help further.
      
 
      Regards,
      Kyle
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Mar 23, 2015 6:25 PM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hi GuiX,
      
 
      Our datasheet figure with the 100 ohm differential termination assumes that the LVPECL receiver is self biased.  The clock buffer figure (2D) is biasing the receiver to a ~2V common mode using an external 3.3V supply and resistor divider and is also setting the input impedance to ~50 ohms (84||125) to match each trace to the receiver.
      
 
      The 100ohm differential resistor is not needed when using the clock buffer termination diagram.  Please let me know if I can help further.
      
 
      Regards,
      Kyle
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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