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AD9517 LVPECL output interface to a fanout buffer

Hello everyone:

I am using one AD9517-0 LVPECL output to drive a fanout buffer to convert the signal to two LDVS signals.

In the AD9517-0 datasheet I can see this figure to interface LVPECL stages:

On the other hand, in the datasheet of the fanout buffer, I can see this other configuration:

My dessign follows the AD recomendation (first schematic) and incorporates R1 to R4 of the second schematic.

Question: Should I keep the 100 Ohn resistor at the imput of the receiver (as proposed in the AD schematic)?

Thanks in advance

Regards

GuiX

  • Hi GuiX,

    Our datasheet figure with the 100 ohm differential termination assumes that the LVPECL receiver is self biased.  The clock buffer figure (2D) is biasing the receiver to a ~2V common mode using an external 3.3V supply and resistor divider and is also setting the input impedance to ~50 ohms (84||125) to match each trace to the receiver.

    The 100ohm differential resistor is not needed when using the clock buffer termination diagram.  Please let me know if I can help further.

    Regards,
    Kyle

  • Dear Guix,

    In the first drawing, we're assuming that the input receiver is providing its own DC biasing. Yes. you can to keep the 100 ohms across the differential pair.

    In the 2nd drawing, the Thevenin equivalent termination not only accomplishes impedance matching, but also DC-biases the input.

    However, if you want to use the LVPECL outputs on the AD9517 to drive LVDS inputs, You can do that by powering VS_LVPECL at 2.5V, and programming the amplitude bits to the min output amplitude. This will make the AD9517 LVPECL drivers compatible with LVDS in terms of amplitude and common mode voltage.

    -Paul

  • Dear Paul and Kyle,

    Thank you very much for your advise.

    1.- Please, let me know if the next schematic is correct (the 100 Ohm resistor is not mounted):

    2.- Paul suggest to use the LVPECL output on the AD9517-0 in a LVDS compatible mode. What is the maximum frequency for this configuration? The AD9517-0 LVDS outputs maximum frequency is 800 MHz.

    Thank you in advance

    Regards

    GuiX

  • Dear GuiX,

    Kyle is correct. The 100ohm resistor marked with the red "X" is not needed and if you include it, you'll cut the amplitude in half.

    For Question 2, the max frequency isn't a simple number. The max speed is governed by the amplitude you require. The LVPECL outputs will toggle at 3 GHz, but waveform will be sinusoidal and the amplitude will be small. Refer to Figure 25 in the datasheet to see the amplitude vs frequency plot. The reason we spec 1.6 GHz is that it's max frequency at which there is enough amplitude so that nearly all LVPECL receivers will still function with good performance.

    The neat part about following my suggestion for driving an LVDS input using an LVPECL output is that you have four amplitude settings to choose from, and it's easy to increase the output driver amplitude in the event that you need to. LVPECL is much better at driving long traces at high frequency than LVDS.

    -Paul

  • Dear Paul and Kyle,

    Thank you very much for your support. Now it is clear.

    Best Regards

    GuiX