EVAL ADI-BERT

Dear Sir,

According to the document UG-551, if it's support the output jitters to 0.4 UI while external clock input (@ 8Gbps,40MHz) in mode 5 ?

Thanks in advance.

UG-551.pdf
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  • 0
    •  Analog Employees 
    on Apr 8, 2015 6:39 AM

    Dear Mr. Chu,

    Do you want to generate a PRBS pattern at 8Gbps, by referring to a 40MHz reference clock

    in "mode 5" configuration, described in UG551?

    If yes, you could have the PRBS pattern output with total  jitter less than 0.4UI,

    given your input reference clock satisfies the specifications defined in ADN2915 datasheet, table 3, and

    the input clock total jitter is 0.6UI or better.

    Best Regards,

    Dongfeng Zhao

Reply
  • 0
    •  Analog Employees 
    on Apr 8, 2015 6:39 AM

    Dear Mr. Chu,

    Do you want to generate a PRBS pattern at 8Gbps, by referring to a 40MHz reference clock

    in "mode 5" configuration, described in UG551?

    If yes, you could have the PRBS pattern output with total  jitter less than 0.4UI,

    given your input reference clock satisfies the specifications defined in ADN2915 datasheet, table 3, and

    the input clock total jitter is 0.6UI or better.

    Best Regards,

    Dongfeng Zhao

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