EVAL ADI-BERT

Dear Sir,

According to the document UG-551, if it's support the output jitters to 0.4 UI while external clock input (@ 8Gbps,40MHz) in mode 5 ?

Thanks in advance.

UG-551.pdf
  • 0
    •  Analog Employees 
    on Apr 8, 2015 6:39 AM

    Dear Mr. Chu,

    Do you want to generate a PRBS pattern at 8Gbps, by referring to a 40MHz reference clock

    in "mode 5" configuration, described in UG551?

    If yes, you could have the PRBS pattern output with total  jitter less than 0.4UI,

    given your input reference clock satisfies the specifications defined in ADN2915 datasheet, table 3, and

    the input clock total jitter is 0.6UI or better.

    Best Regards,

    Dongfeng Zhao

  • Dear Mr. Zhao,

    Thanks for your quick reply. Due to DUT test condition request, would like to know if the jitters of PRBS output can meet 0.4 UI under 8Gbps while external clock input at 40 MHz which including jitters in mode 5 ?

    Thanks.

  • 0
    •  Analog Employees 
    on May 12, 2015 7:13 PM

    Dear Kenton,

    In a conservative way, I would say no, because the CDR recovered outputs, in the mode 5 case, could have the reference clock jitter "superimposed on" to ADN2915 generated jitters, after locked to the reference.

    Therefore, to answer your question, what is your 40MHz clock jitter performance?

    If your 40MHz clock is a crystal clean clock source, yes, ADN2915 will deliver an recovered 8Gbps PRBS

    data with less than 0.4UI as you expected.

    Hope these are what you need.

    Best Regards,

    Dongfeng Zhao

  • 0
    •  Analog Employees 
    on Aug 2, 2018 2:59 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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