AD9518 Sync

I Have two Ad9518's in different slots of my system that have the same 10mhz input clock in common. Both AD9518's are also configured to generate a 400Mhz clock on output 0&1. I'm trying to figure out how to phase align the outputs and I figured that since the 400Mhz was an integer multiple of the 10Mhz input the both outputs would be phase aligned. I've also tried to enable (via csr write) and toggle the external sync pin without any luck. Are there any tips to phase align the outputs?

  • Hi Frank,

    Are you seeing that the outputs are phase locked but that there is a fixed phase offset?

    When you issue SYNC signals to two separate parts, you cannot guarantee that the SYNC occurs at the same high speed clock edge from the VCO RF divider output.  Even though the high speed edges are phase aligned to the reference input, there are many intermediate high frequency edges that the distribution dividers can use as its starting point so multiple SYNC events will result in different phase relationships between parts.  To eliminate the ambiguity of SYNC signal to internal high speed clock timing, you really want to use a part that has zero delay which forces the output rising edge to be coincident with the input rising edge.  The AD9518 unfortunately does not support zero delay but a similar part (AD9520) does.  Zero delay will automatically compensate for any divider phase mismatch across parts.

    http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/ad9520-0.html


    When using zero delay there are a few things to consider:

    1. The output of each PLL will attempt to phase align to the reference input rising edge, therefore you need your reference rising edges to occur at the same point in time at each part.
      1. Typically the reference dividers are not SYNC'ed with respect to the output dividers so you will want to bypass this in both parts.
    2. The output used for zero delay must be the lowest integer division of all other outputs.  For example if you had 400MHz, 100MHz and 50MHz outputs, your zero delay feedback path could be 50MHz or 25MHz.

    Let me know if I can clarify anything.

    Regards,
    Kyle