I need to synthesize a 135 MHz very low-phase noise differential (LVDS or LVPECL) clock for my present application.
The AD9575 looks like a convenient choice, though the datasheet indicates that it wants one of three specific reference clocks/crystals as input. From my calculations, in its 6.25 or 6.375 multiplier ratios, it will generate 135 MHz given a 21.6 MHz or 21.17 MHz clock input.
Question: will this work?
Second question: this device is specified for a maximum reference input of 25.78 MHz -- would it tolerate 27 MHz? Used the times 5 mode, this would also meet my requirements.
Advice is appreciated.
[Data Sheet attached for your convenience]