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AD9516 reference spurs

Dear All,

I am using the AD9516-0 to clock the AD9122.

  • reference frequency = 122.88MHz
  • DAC sampling = 983.04MHz
  • PFD frequency = 61.44MHz

Around the 983.04MHz, I can observe a lot of spurs every 61.44MHz.

What is the maximum reference spurious level for the AD9516?

Thank you


  • Hi Christophe,

    > What is the maximum reference spurious level for the AD9516?

    There is no maximum. You could have enormous spurs if you set the loop BW high enough and the PFD low enough.

    That said, one very easy way to get charge pump spurs is to have an extremely high loop BW. Therefore, reducing the charge pump current to drop the loop BW is one way to help fix the issue. By the way, what is the spur level?

    One way to get bad spurs is to solder new components down in the loop filter and not clean and wash the flux off the components.

    Another source of spurs is programming REFMON, LD, or STATUS to a dynamic signal like the R divider output.

    -Paul Kern

  • Hello Paul,

    Thank you for your quick reply.

    Below is the Spectrum for a large sweep that I could measure from one of the 983.04MHz LVEPCL differential output. You can observe the spurs every 61.44MHz (PFD frequency / 2 ).

    • The PFD frequency is 61.44MHz (R=2)
    • The loop filter is very low compare to PFD (166kHz from ADiSimCLK)
    • Internal VCO frequency = 3 * 983.04MHz = 2949.12MHz

    From this clock signal, the DAC output is fine but I was wondering if what I am observing at the AD9516 output is a normal behavior. I will double check your different coments.

    Thank you again.

    PS: Everytime I reprogramm the chip, the level of the spurs change


  • Hi Christophe,

    I'm on the road at the moment, but hope to look at this later today. I apologize for the delay, but I'd to let you know that I haven't forgotten about you.

    -Paul Kern

  • I'm bothered that the level changes every time you reprogram the chip.

    I don't know which loop filter you're using, but if I use the default for the AD9516-3, and set the charge pump current to its minimum value (0.6mA), I get a closed loop BW of 140 kHz, 50 deg of phase margin, and CP spur that's -159 dBc,

    This filter is: (from the CP pin to the LF pin:

    1st shunt C:     1.2 nF

    Series R-C in parallel with the first shunt C: 750 ohms and 0.01uF

    Final shunt C: 150 pF.

    Are you sure you don't have any dynamic signals activated on the status pins?

    Also, which input reference mode are you using? Could it be that you have a CMOS ref input that's coupling through to the outputs?

    -Paul Kern

  • Hello Paul,

    I was wondering if you have some comments regarding the screen shot that I posted on the forum. Here are two measurements on another board. All the spurs are under -80dBm.

    Thank you.



  • Hi Christophe,

    Before going further, I wanted to point out that you'll have better phase noise using the AD9516-3 and a VCO frequency of 1966 MHz.

    I haven't looked at wideband SFDR plots in a long time, but I'm surprised that the spurs are only -60 dBc.  However, it's impossible to get a ref spur better than about -90 dBc on our eval board even with the power off as the input clock couples through the board. Therefore, it's entirely possible that your plot normal. What does the SFDR plot look like with the charge pump tri-stated?

    The other bothersome thing that I see is that the phase noise plot isn't as good as it should be, but this could be a limitation of your equipment. The floor should be a lot better than -126 dBc/Hz and you have some peaking in your transfer function at a 28.6 kHz offset.

    Btw, I'm going to be traveling on business next week, so expect slow replies.


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