i wonder if the RMS voltage noise of the ADCLK905 family of chips can be calculated from the specifications. More specifically: If i apply a constant input signal, what is the output voltage RMS noise in the frequency range of 0-100MHz (assuming a prefect low pass)?
I hope this can be calculated from the specification of: -161 dbc/Hz phase noise, but i am not very familiar with this quantity. Is the following calculation sensible?
-161 dbc/Hz * 100MHz = 10e-16 * 10e8 = 10e-8 in units of signal to noise power.
Voltage noise is then sqrt(10e-8) = 10e-4
The output signal voltage is 800mV, so the RMS noise 800mV * 10e-4 = 0.4 µV
0.4 µV rms noise seems very low for a chip that is optimized for fast transitions, so i assume i made an error..
I hope this made sense. Any help is greatly appreciated.