ADCLK854 Clock buffer phase noise


I want to estimate 40MHz phase noise of ADCLK854 from datasheet fig.12.  I found a similar discussion in engineer zone.

My first question.

If input slew rate was not an issue at 40MHz and phase noise is -132dBc/Hz @ 1Khz offset. The buffer output phase noise will be ( -117dBc/Hz – 28db )= -145 dBc/Hz, So the output phase noise is better than input. Is that right?

2nd question,

Is it possible to calculate LVDS output phase noise when input signal is : 40MHz LVPECL phase noise = -142 dBc/Hz @ 1KHz offset ?


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