1800 MHz and 900 MHz synchronously generation by AD9520-3 internal VCO

Hi,

I would like to generate 1800 MHz and 900 MHz clocks by using internal VCO which is built-in AD9520-3.

Datasheet contains following information.

But in the same time.

Could I synchronously generate 1800 MHz and 900 MHz by AD9520-3 internal VCO which is set on 1.8 GHz and then distributed to channel dividers as shown below?

Or you can offer any other solution?

Regards,

Ivan

  • 0
    •  Analog Employees 
    on Nov 9, 2015 11:13 AM

    Hi nealw,

    Thank you for the explanation.

    Regards,

    Ivan

  • 0
    •  Analog Employees 
    on Nov 9, 2015 6:58 PM

    Hi Ivan,

    The configuration you have shown above does not violate any of the frequency specifications in the datasheet. The maximum frequency for the channel dividers to fully function is 1.6 MHz, but it is stipulated that if divides of 3 and 17 are excluded from operation, then 2 GHz can be used for this limit.

    Unfortunately, this device does not support operation as a free run oscillator. This is due to the required VCO calibration to select the appropriate band for a 1800 MHz operating frequency. The calibration requires an external frequency source and appropriate PLL configuration in order to find the correct result. Also, the result will vary from part to part due to process variations. I suggest that you use a cheap XTAL as the reference input and configure the PLL settings to give you a 1800 MHz VCO frequency. All other solutions I could suggest still involve an external XTAL.

  • 0
    •  Analog Employees 
    on Nov 10, 2015 10:01 AM

    Hi nealw,

    Could please you clarify following?

    AD9520-3 contains a table below.

    So provided earlier mode is not valid for the AD9520-3.

    Only way to generate 1.8 GHz and 0.9 GHz is using VCO direct to output for 1.8 GHz and one of dividers for 0.9 GHz.

    So I have a question.

    How could 1.8 GHz and 0.9 GHz outputs be synchronized in this case?

    Regards,

    Ivan

  • 0
    •  Analog Employees 
    on Nov 10, 2015 10:52 AM

    Hi Neil,

    Thank you for the answer. I will wait until you clarify it with datasheet owner. Thank you.

    Regards,

    Ivan

  • 0
    •  Analog Employees 
    on Nov 10, 2015 6:41 PM

    Hi Ivan,

    That does seem to be a weird nuance of this part. In this case, the synchronization between the two outputs is implicit, as they represent the input and output of a single divider. The divider only transitions on a rising edge at it's input, therefore a rising edge produced on it's output is synchronous with an input rising edge, offset by the propagation delay of the divider.

    Said propagation delay doesn't seem to be explicitly stated in the datasheet, but the in the specification for tpecl, the difference between "High frequency clock distribution path configuration" and the "Clock distribution configuration" numbers seems as though it would represent this value. I will have to check with the datasheet owner to be sure, but he is out of the office for the remainder of this week.