AD9522-1 REF IN Clock

Question

Hi, 
 Looking for a support on AD9522-1 input reference clock. We are using singled ended reference clock[one from FPGA, one from oscillator], with AC coupling and AD9522 internal DC offset is off. 
 When we probed on the REF_IN pin, there is a -0.4V offset in the clock signal. Can you please check it? 
 Attaching the schematic and waveform of the corresponding section. 
 Thank you, 
 Regards, 
 Sneha

ADIApproved · Accepted Answer

Hello Sneha, 
 This behavior is expected. When in AC-coupled, single-ended mode, the user must either use the internal DC-bias mode or provide DC-biasing so that the input clock goes from 0 to 3.3V. 
 The reason we added the DC-bias mode to the SE input is to avoid this issue. 
 -Paul Kern)

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AD9522-1 REF IN Clock