I just only use Ref A(19.2MHz), left the RefB/RefC/RefD open (I just put the 0.01MHz for refb due to the GUI ask for 1 input for the other 3Ref input), 4chanel total 8port output 167.33166MHz, the following fig shows, system clock is 49.152Mhz
Does these setting work for board?
this is 49.152MHz system clk (I just get the single-end data,which is differetial input)
here is the 19.2MHz clk for the Ref A input
we am just debug the board use the AD9554 for the OTU2 ref clock, the processor could access AD9554 by I2C port. and could get the Device ID, also could read and write Reg 0x200 and 0x201 ..
we don't use the EPROM, so left the M-pin open.
we just set the register from register0x200~register0x365.
But there are no output clk at the portA/B/C, Is there any other setting we need to config to get the output clock from AD9554?
we use the wizard to get the NonDefault register map(111 nondefault reg), last pic shows. we only could set part of these reg, such as Reg0x200,Reg0x204,~reg0x346, while we can not set the other regs, from 0x400 to the end,
any clue why we can not change the nondefault register setting?
Is there any setting we should pay more attention?
Thank you in advance
You need to be sure to issue an IO Update, by writing R0x000F = 0x01, before reading back the status registers. Not all status registers are live. Issuing the IO Update causes the most recent status value of the part to be latched into the status registers for user read back. Many of the above register read backs contain contradicting information between the live status registers and the buffered status registers.
In the unlock case, the DPLL is locked but the APLL is unlocked. The DPLL has a much wider tuning range than the APLL. This is indicative of either a mistake programming the device's dividers (DPLL dividers or R divider typically) or a reference input clock or system clock that is very inaccurate. I don't think it is your reference clock or system clock, because the DPLL tuning word history for the working case shows < 1 ppm offset from ideal.
You can try masking the sync for the four channels by writing:
R0x0436 = 0x7
R0x0536 = 0x7
R0x0636 = 0x7
R0x0736 = 0x7
R0x000F = 0x1
This should make it such that you always see an output clock.
Is their anyway you log the exact register writes and reads and provide them to me? You can attach a file by clicking the "Use advanced editor" link in the upper right hand corner of the reply box.
we do issue the IO update in the script after register download to the chip.
After masking the sync, we could measure the output clock..
now we find after soft sync all( 0xa00=0xc,IO update) , we could get the output without mask the sync ,
eg0xd01 = F3
Reg0xd02 = 0xF8
Reg0xd20 = 0x0F
Reg0xd21 = 0x00
Reg0xd22 = 0x01
Reg0xd23 = 0xec
Reg0xd24 = 0x5e
Reg0xd25 = 0x4b
Reg0xd26 = 0x21
now we find after soft sync all( 0xa00=0x2;IO update, then0xa00=0x4; IO update) , we could get the output without mask the sync .
( 0xa00=0xc,IO update) soft sync is normal operation step? please confirm ,
I tried to upload file, while still can not upload in the topic discussion( can not find "Use advanced editor"), just start a new discussion and send it to you(title is "Description about the AD9554 output issue for NeilW") , please review it.
Thanks so much.
The typically the register writes would be to issue the 'calibrate all' command, IO update, issue the 'soft sync all' command while clearing the 'calibrate all' bit, IO Update and then clear the soft sync bit and IO Update:
Write R0xA00 = 0x02 (set calibrate all bit)
Write R0x00F = 0x01 (IO Update)
Write R0xA00 = 0x08 (set soft sync all bit, clear calibrate all bit)
Write R0xA00 = 0x00 (clear soft sync all bit)