I just only use Ref A(19.2MHz), left the RefB/RefC/RefD open (I just put the 0.01MHz for refb due to the GUI ask for 1 input for the other 3Ref input), 4chanel total 8port output 167.33166MHz, the following fig shows, system clock is 49.152Mhz
Does these setting work for board?
this is 49.152MHz system clk (I just get the single-end data,which is differetial input)
here is the 19.2MHz clk for the Ref A input
we am just debug the board use the AD9554 for the OTU2 ref clock, the processor could access AD9554 by I2C port. and could get the Device ID, also could read and write Reg 0x200 and 0x201 ..
we don't use the EPROM, so left the M-pin open.
we just set the register from register0x200~register0x365.
But there are no output clk at the portA/B/C, Is there any other setting we need to config to get the output clock from AD9554?
we use the wizard to get the NonDefault register map(111 nondefault reg), last pic shows. we only could set part of these reg, such as Reg0x200,Reg0x204,~reg0x346, while we can not set the other regs, from 0x400 to the end,
any clue why we can not change the nondefault register setting?
Is there any setting we should pay more attention?
Thank you in advance
After configuring the device and letting the DPLLs lock, could you please execute an IO Update by writing R0x000F = 0x01 and then read back R0x0D01 - R0x0D02, R0x0D20 - R0x0D26, and R0x0D40 - R0x0D46 and let me know what their values are, please?