Please Help:  how to get the clk out from the AD9554

I just only use Ref A(19.2MHz), left the RefB/RefC/RefD open (I just put the 0.01MHz for refb due to the GUI ask for 1 input for the other 3Ref input),  4chanel total 8port output 167.33166MHz, the following fig shows, system clock is 49.152Mhz

Does these setting work for board?

this is 49.152MHz system clk (I just get the single-end data,which is differetial input)

here is the 19.2MHz clk for the Ref A input

   we am just debug the board use the AD9554 for the OTU2 ref clock,   the processor could access AD9554 by I2C port. and could get the Device ID, also could read and write Reg 0x200 and 0x201 ..

we don't  use the EPROM, so left the M-pin open.

we just set the register from register0x200~register0x365.

But there are no output clk at the portA/B/C, Is there any other setting we need to config to get the output clock from AD9554?

  

  

     we use the wizard to get the NonDefault register map(111 nondefault reg), last pic shows.  we only could set part of these reg, such as Reg0x200,Reg0x204,~reg0x346,  while we can not set the other regs,  from 0x400 to the end,

any clue why we can not change the nondefault register setting?

Is there any setting we should pay more attention?

Thank you in advance

  

 

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    •  Analog Employees 
    on Dec 9, 2015 8:20 PM

    Hi,

    It seems as though you have not executed any of the operational control operations. Therefore, none of the PLLs have locked. I recommend that you append the following writes to your sequence:

    Write R0x0A00 = 0x02

    Write R0x000F = 0x01

    Write R0x0A00 = 0x04

    Write R0x000F = 0x01

    Write R0x0A00 = 0x00

    Write R0x000F = 0x01

     

    This will issue a 'calibrate all' command and then a 'sync all' command.

     

    The reason you believe you are not able to write registers above R0x400 is because they are on the system clock domain and the system clock must be locked in order transfer their content from the buffered domain to the active domain. By default the serial port reads from the active domain, but you can read from the buffered domain by setting R0x0001[5] = 1. Doing so and reading R0x400 and above will allow you to confirm the write prior to the system clock locking.

    Note: It is much more useful if you upload a setup file with the register content rather than just a screenshot.

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  • 0
    •  Analog Employees 
    on Dec 9, 2015 8:20 PM

    Hi,

    It seems as though you have not executed any of the operational control operations. Therefore, none of the PLLs have locked. I recommend that you append the following writes to your sequence:

    Write R0x0A00 = 0x02

    Write R0x000F = 0x01

    Write R0x0A00 = 0x04

    Write R0x000F = 0x01

    Write R0x0A00 = 0x00

    Write R0x000F = 0x01

     

    This will issue a 'calibrate all' command and then a 'sync all' command.

     

    The reason you believe you are not able to write registers above R0x400 is because they are on the system clock domain and the system clock must be locked in order transfer their content from the buffered domain to the active domain. By default the serial port reads from the active domain, but you can read from the buffered domain by setting R0x0001[5] = 1. Doing so and reading R0x400 and above will allow you to confirm the write prior to the system clock locking.

    Note: It is much more useful if you upload a setup file with the register content rather than just a screenshot.

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