Please Help:  how to get the clk out from the AD9554

I just only use Ref A(19.2MHz), left the RefB/RefC/RefD open (I just put the 0.01MHz for refb due to the GUI ask for 1 input for the other 3Ref input),  4chanel total 8port output 167.33166MHz, the following fig shows, system clock is 49.152Mhz

Does these setting work for board?

this is 49.152MHz system clk (I just get the single-end data,which is differetial input)

here is the 19.2MHz clk for the Ref A input

   we am just debug the board use the AD9554 for the OTU2 ref clock,   the processor could access AD9554 by I2C port. and could get the Device ID, also could read and write Reg 0x200 and 0x201 ..

we don't  use the EPROM, so left the M-pin open.

we just set the register from register0x200~register0x365.

But there are no output clk at the portA/B/C, Is there any other setting we need to config to get the output clock from AD9554?

  

  

     we use the wizard to get the NonDefault register map(111 nondefault reg), last pic shows.  we only could set part of these reg, such as Reg0x200,Reg0x204,~reg0x346,  while we can not set the other regs,  from 0x400 to the end,

any clue why we can not change the nondefault register setting?

Is there any setting we should pay more attention?

Thank you in advance

  

 

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  • 0
    •  Analog Employees 
    on Dec 9, 2015 8:20 PM

    Hi,

    It seems as though you have not executed any of the operational control operations. Therefore, none of the PLLs have locked. I recommend that you append the following writes to your sequence:

    Write R0x0A00 = 0x02

    Write R0x000F = 0x01

    Write R0x0A00 = 0x04

    Write R0x000F = 0x01

    Write R0x0A00 = 0x00

    Write R0x000F = 0x01

     

    This will issue a 'calibrate all' command and then a 'sync all' command.

     

    The reason you believe you are not able to write registers above R0x400 is because they are on the system clock domain and the system clock must be locked in order transfer their content from the buffered domain to the active domain. By default the serial port reads from the active domain, but you can read from the buffered domain by setting R0x0001[5] = 1. Doing so and reading R0x400 and above will allow you to confirm the write prior to the system clock locking.

    Note: It is much more useful if you upload a setup file with the register content rather than just a screenshot.

  • Neil

       Thank you for response and explanation.

        I tried the operation based on your recommendation, it do works for 2 output channel(chanel 0 and channel 2 could locked), while the other 2 channel not locked(system clk locked, DLL locked , APLL not locked).

        Any clue about the 2 channel out of lock?

        all the register setting is as following shows(Sorry I don't find how to upload file, just copy all the setting I use):

    we only have one ref clock(19.2MHz) to the REFA, the other 3 ref clk input(REFB/REFC/REFD) are open(not connect), system input clk is 49.152MHz. the 19.2MHz input and 49.152MHz wavform please refer to the yesterday's post.

    <detailed setup information>
    -- System Clock --
        Input Freq: 49.152 MHz
        Input Type: Crystal Resonator
        J: x2
        Pfd Freq: 98.304 MHz
        K: 24
        VCO Freq: 2.359296 GHz
    ------------------
    -- Reference Inputs --
    - Ref A -    Input Freq: 19.2 MHz
        Ra: 96
        Dpfd Freq: 200.0 kHz
    - Ref B -    Input Freq: 19.44 MHz
        Rb: 1
        Dpfd Freq: 19.44 MHz
    - Ref C -    Input Freq: 19.44 MHz
        Rc: 1
        Dpfd Freq: 19.44 MHz
    - Ref D -    Input Freq: 19.44 MHz
        Rd: 1
        Dpfd Freq: 19.44 MHz
    ----------------------
    -- Channel 0 --
    - Dpll -
       Ref A
        N 0a: 1,568
        Frac 0a: 58
        Mod 0a: 79
        LBW 0a: 50.0
       Ref B
        N 0b: 1
        Frac 0b:
        Mod 0b:
        LBW 0b: 50.0
       Ref C
        N 0c: 1
        Frac 0c:
        Mod 0c:
        LBW 0c: 50.0
       Ref D
        N 0d: 1
        Frac 0d:
        Mod 0d:
        LBW 0d: 50.0
       DCO
        Int 0: 7
        FTW 0: 558,071,270
    - Apll -
        Apfd 0 Freq: 313.746835 MHz
        M 0: 8
        VCO 0 Freq: 2,509.974683 MHz
        P 0: 3
        Qa 0: 5
        Out 0A Freq: 167.331646 MHz
        Qb 0: 5
        Out 0B Freq: 167.331646 MHz
    ---------------
    -- Channel 1 --
    - Dpll -
       Ref A
        N 1a: 1,521
        Frac 1a: 171
        Mod 1a: 869
        LBW 1a: 50.0
       Ref B
        N 1b: 1
        Frac 1b:
        Mod 1b:
        LBW 1b: 50.0
       Ref C
        N 1c: 1
        Frac 1c:
        Mod 1c:
        LBW 1c: 50.0
       Ref D
        N 1d: 1
        Frac 1d:
        Mod 1d:
        LBW 1d: 50.0
       DCO
        Int 1: 7
        FTW 1: 810,392,021
    - Apll -
        Apfd 1 Freq: 304.239356 MHz
        M 1: 11
        VCO 1 Freq: 3,346.632911 MHz
        P 1: 4
        Qa 1: 5
        Out 1A Freq: 167.331646 MHz
        Qb 1: 5
        Out 1B Freq: 167.331646 MHz
    ---------------
    -- Channel 2 --
    - Dpll -
       Ref A
        N 2a: 1,568
        Frac 2a: 58
        Mod 2a: 79
        LBW 2a: 50.0
       Ref B
        N 2b: 1
        Frac 2b:
        Mod 2b:
        LBW 2b: 50.0
       Ref C
        N 2c: 1
        Frac 2c:
        Mod 2c:
        LBW 2c: 50.0
       Ref D
        N 2d: 1
        Frac 2d:
        Mod 2d:
        LBW 2d: 50.0
       DCO
        Int 2: 7
        FTW 2: 558,071,270
    - Apll -
        Apfd 2 Freq: 313.746835 MHz
        M 2: 16
        VCO 2 Freq: 5,019.949367 MHz
        P 2: 5
        Qa 2: 6
        Out 2A Freq: 167.331646 MHz
        Qb 2: 6
        Out 2B Freq: 167.331646 MHz
    ---------------
    -- Channel 3 --
    - Dpll -
       Ref A
        N 3a: 1,608
        Frac 3a: 984
        Mod 3a: 1,027
        LBW 3a: 50.0
       Ref B
        N 3b: 1
        Frac 3b:
        Mod 3b:
        LBW 3b: 50.0
       Ref C
        N 3c: 1
        Frac 3c:
        Mod 3c:
        LBW 3c: 50.0
       Ref D
        N 3d: 1
        Frac 3d:
        Mod 3d:
        LBW 3d: 50.0
       DCO
        Int 3: 7
        FTW 3: 356,214,669
    - Apll -
        Apfd 3 Freq: 321.791626 MHz
        M 3: 13
        VCO 3 Freq: 4,183.291139 MHz
        P 3: 5
        Qa 3: 5
        Out 3A Freq: 167.331646 MHz
        Qb 3: 5
        Out 3B Freq: 167.331646 MHz
    ---------------
    </detailed setup information>

    <registers>
    Register (Hex), Value (Hex), Value (Dec)
    0x200,  0x18,  24
    0x201,  0x09,  9
    0x204,  0xEE,  238
    0x205,  0x02,  2
    0x301,  0x5F,  95
    0x304,  0x85,  133
    0x305,  0xBA,  186
    0x306,  0x1A,  26
    0x307,  0x03,  3
    0x400,  0xE6,  230
    0x401,  0x7D,  125
    0x402,  0x43,  67
    0x403,  0x21,  33
    0x431,  0x08,  8
    0x434,  0x03,  3
    0x438,  0x04,  4
    0x43c,  0x04,  4
    0x440,  0x01,  1
    0x441,  0xF4,  244
    0x442,  0x01,  1
    0x444,  0x1F,  31
    0x445,  0x06,  6
    0x447,  0x3A,  58
    0x44a,  0x4F,  79
    0x44e,  0xF4,  244
    0x44f,  0x01,  1
    0x45b,  0xF4,  244
    0x45c,  0x01,  1
    0x468,  0xF4,  244
    0x469,  0x01,  1
    0x500,  0xD5,  213
    0x501,  0x99,  153
    0x502,  0x4D,  77
    0x503,  0x30,  48
    0x531,  0x0B,  11
    0x534,  0x04,  4
    0x538,  0x04,  4
    0x53c,  0x04,  4
    0x540,  0x01,  1
    0x541,  0xF4,  244
    0x542,  0x01,  1
    0x544,  0xF0,  240
    0x545,  0x05,  5
    0x547,  0xAB,  171
    0x54a,  0x65,  101
    0x54b,  0x03,  3
    0x54e,  0xF4,  244
    0x54f,  0x01,  1
    0x55b,  0xF4,  244
    0x55c,  0x01,  1
    0x568,  0xF4,  244
    0x569,  0x01,  1
    0x600,  0xE6,  230
    0x601,  0x7D,  125
    0x602,  0x43,  67
    0x603,  0x21,  33
    0x631,  0x10,  16
    0x634,  0x05,  5
    0x638,  0x05,  5
    0x63c,  0x05,  5
    0x640,  0x01,  1
    0x641,  0xF4,  244
    0x642,  0x01,  1
    0x644,  0x1F,  31
    0x645,  0x06,  6
    0x647,  0x3A,  58
    0x64a,  0x4F,  79
    0x64e,  0xF4,  244
    0x64f,  0x01,  1
    0x65b,  0xF4,  244
    0x65c,  0x01,  1
    0x668,  0xF4,  244
    0x669,  0x01,  1
    0x700,  0x8D,  141
    0x701,  0x67,  103
    0x702,  0x3B,  59
    0x703,  0x15,  21
    0x731,  0x0D,  13
    0x734,  0x05,  5
    0x738,  0x04,  4
    0x73c,  0x04,  4
    0x740,  0x01,  1
    0x741,  0xF4,  244
    0x742,  0x01,  1
    0x744,  0x47,  71
    0x745,  0x06,  6
    0x747,  0xD8,  216
    0x748,  0x03,  3
    0x74a,  0x03,  3
    0x74b,  0x04,  4
    0x74e,  0xF4,  244
    0x74f,  0x01,  1
    0x75b,  0xF4,  244
    0x75c,  0x01,  1
    0x768,  0xF4,  244
    0x769,  0x01,  1
    0xFFF,  0xF9,  249
    0x1488,  0x03,  3
    0x1588,  0x03,  3
    0x1688,  0x03,  3
    0x1788,  0x03,  3
    0xF,  0x01,  1
    0xFFF,  0x00,  0
    </registers>

    <frequencies>
    19200000;19440000;19440000;19440000;49152000
    </frequencies>

    <ftwfreq>
    155520000;19440000;19440000;19440000;155520000;155520000;155520000;155520000;49.152
    </ftwfreq>

    <ftwfecref>
    10;81;1;1;1;1;1;1
    </ftwfecref>

    <ftwfecout>
    85;79;1;1;85;79;1;1;85;79;1;1;85;79;1;1
    </ftwfecout>

    <ftwenref>
    True;True;True;True;False;False;False;False;False;False;False;False;False;False;False;False;True
    </ftwenref>

    <ftwlbwref>
    50;50;50;50
    </ftwlbwref>

    <ftwselref>
    0;1;1;1
    </ftwselref>

  • 0
    •  Analog Employees 
    on Dec 10, 2015 11:28 PM

    After configuring the device and letting the DPLLs lock, could you please execute an IO Update by writing R0x000F = 0x01 and then read back R0x0D01 - R0x0D02, R0x0D20 - R0x0D26, and R0x0D40 - R0x0D46 and let me know what their values are, please?

  • Neil

      Here is the operation step and reg check result.

       Initially, we configure the chip step by step manually based on the .stp file(include  'calibrate all' command and then a 'sync all'), which I sent here yesterday,  which looks the ref clk quality is not good

    then check the reg value as you mentioned:

    Reg0xd01  = 0x03 , sometimes its Reg0xd01  = C3

    Reg0xd02  = 0x07

    Reg0xd20  = 0x06

    Reg0xd21  = 0x01

    Reg0xd22  = 0x02

    Reg0xd23  = 0x00

    Reg0xd24  = 0x00

    Reg0xd25  = 0x00

    Reg0xd26  = 0x00

       secondly, we configure the chip aotumaticlly using script(include  'calibrate all' command and then a 'sync all') based the same .stp file,  which looks the ref clk quality is not good while still could locked, (initially mannaully input maybe typo )

    then check the reg value : Reg0x40~46 is same as Reg0x20~0x26

    Reg0xd01  = 0xF3

    Reg0xd02  = 0x07

    Reg0xd20  = 0x0f

    Reg0xd21  = 0x01

    Reg0xd22  = 0x00

    Reg0xd23  = 0x00

    Reg0xd24  = 0x00

    Reg0xd25  = 0x00

    Reg0xd26  = 0x00

      Today , after configure the chip automaticlly(include  'calibrate all' command and then a 'sync all'),  then manually  calibrate all and sync all (manually input the command as you sugguest before:  rite R0x0A00 = 0x02

    Write R0x000F = 0x01; write R0x0A00 = 0x04; write R0x000F = 0x01;Write R0x0A00 = 0x00;Write R0x000F = 0x01), then check the register again. now looks the chip 4channel all locked, as the following reg show, Could you please confirm the chip work ok now?

    Reg0xd01  = 0xF3

    Reg0xd02  = 0xF8

    Reg0xd20  = 0x0F

    Reg0xd21  = 0x00

    Reg0xd22  = 0x01

    Reg0xd23  = 0xa4

    Reg0xd24  = 0x92

    Reg0xd25  = 0x42

    Reg0xd26  = 0x21

    Reg0xd40  = 0x0F

    Reg0xd41  = 0x00

    Reg0xd42  = 0x01

    Reg0xd43  = 0xa3

    Reg0xd44  = 0xa7

    Reg0xd45  = 0x4c

    Reg0xd46  = 0x30

    Reg0xd02 = 0xf8, means,bit[3] = 1means REFA valid  This bit is 1 if the REFA frequency is within the programmed limits and the validation timer has expired.

          what is "the validation timer has expired", Could you please explane what the timer expired means, and how to improve it.

         Thank you so much for the patient support and help.

  • Hi, Neil

        after check the reg value of the chip,it looks all the PLL locked, we use the osilliscope to test the output, no signal at the 4channel, any frequncy signal, not there

    Reg0xd01  = 0xF3

    Reg0xd02  = 0xF8

    Reg0xd20  = 0x0F

    Reg0xd21  = 0x00

    Reg0xd22  = 0x01

    Reg0xd23  = 0xa4

    Reg0xd24  = 0x92

    Reg0xd25  = 0x42

    Reg0xd26  = 0x21

    Reg0xd40  = 0x0F

    Reg0xd41  = 0x00

    Reg0xd42  = 0x01

    Reg0xd43  = 0xa3

    Reg0xd44  = 0xa7

    Reg0xd45  = 0x4c

    Reg0xd46  = 0x30

    while we configure the reg manually, then check the reg, find the PLL not lock, as the following reg shows, while

    at the output, oscilliscope could measure the frequncy signal.

    Reg0xd01  =  C3

    Reg0xd02  = 0x07

    Reg0xd20  = 0x06

    Reg0xd21  = 0x01

    Reg0xd22  = 0x02

    Reg0xd23  = 0x00

    Reg0xd24  = 0x00

    Reg0xd25  = 0x00

    Reg0xd26  = 0x00

     

    Then tried the command  'calibrate all' command and then a 'sync all'. then check the reg,

    Reg0xd01  =  C3

    Reg0xd02  = 0x07

    Reg0xd20  = 0x06

    Reg0xd21  = 0x01

    Reg0xd22  = 0x01

    Reg0xd23  = 0xa3

    Reg0xd24  = 0x44(can nor remember value)

    Reg0xd25  = 0x35 (can nor remember value)

    Reg0xd26  = 0x00 (can nor remember value)

    there are still have the signal at the output.

    lease help, when LOCKed,no output, when out of locked, do have some output signal.

    what happen to the setting?

    Thans,  Jizhong