I am using AD9520-3 for clock generation on my custom board. Input reference clock is 10MHz OXCO output with -155dBc/Hz phase noise (PN) at 10KHz offset. I am setting AD9520-3 VCO to 1800MHz and divide by 2 to get 900MHz provided to channels. I am generating 90MHz and 100MHz CMOS clock outputs by using channel dividers.
In ADISimCLK program, it shows that with wideband loop filter, 90MHz output signal's PN value would be around -130dBc/Hz at 10KHz offset (I set the PN values of Ref Sources in ADISimCLK). However in measurements, PN is areound -120dBc/Hz. This 10dBc/Hz error is critical for my design. Using narrowband loop filter such as 3KHz is even worsening the PN value as AD9520-3 VCO PN becomes dominant.
What is the source of this 10dBc/Hz PN difference between measurements and simulation? What are the techniques to improve PN of AD9520-3 outputs? If there is none, is there any other IC which can be replaced with AD9520-3 which has better PN value at 10KHz offset and further?
Thanks in advance