Pogramming the AD9517-4

My design is based on the reference design: UG-328-DesignSupport from Analog Devices, Basically it consist of a AD9517-4, and the AD9253. In my design I program the different blocks from a Zynq FPGA.

I am trying to program the AD9517-4 with no completelly success. I can play arround with the LD, REFMON, and STATUS pins, mor¡nitoring different internal signals, so this proves my SPI bus is working OK. However PLL (AD9517-4) does not look.

Although I know the PLL (AD9517-4) is not locked I play around, doing:

My reference signal is 10MHz that is connected to REF1 (pin 48) and to CLK  (pin 11).

If I set CLK as source:

"01E1","00000000","00"

then I can se the CLK signal internaly divided (VCO DIV = 3 and DIVIDER0 =7) in the output 0 (pins 41 and 42) a signal of 476,2kHz (as it is supposed to be)

if I select VCO (1500MHz) as source (VCO DIV = 3 and DIVIDER0 =7)

"01E1","00000010","02"

i get no signal at all, just zero volts. Even though the PLL is not locked I should se a frequency division of the not locked PLL, shouldn´t I?

The VCO cal is another mistery this is my programming file

"0000","00011000","18"

"0001","00000000","00"

"0002","00010000","10"

"0003","11010011","D3"

"0004","00000000","00"

"0010","00111100","3C"

"0011","00000001","01"

"0012","00000000","00"

"0013","00000110","06"

"0014","00001001","09"

"0015","00000000","00"

"0016","01000101","45"

"0017","10001100","8C"

"0018","00000111","07"

"0019","00001001","09"

"001A","01100011","63"

"001B","11100011","E3"

"001C","00100010","22"

"001D","00001000","08"

"001E","00000000","00"

"001F","00001110","0E"

"00A0","00000000","00"

"00A1","00000000","00"

"00A2","00000000","00"

"00A3","00000000","00"

"00A4","00000000","00"

"00A5","00000000","00"

"00A6","00000000","00"

"00A7","00000000","00"

"00A8","00000000","00"

"00A9","00000000","00"

"00AA","00000000","00"

"00AB","00000000","00"

"00F0","00001100","0C"

"00F1","00001100","0C"

"00F4","00001000","08"

"00F5","00001000","08"

"0140","01000010","42"

"0141","01000010","42"

"0142","01000010","42"

"0143","01001010","4A"

"0190","00110010","32"

"0191","00000000","00"

"0192","00000000","00"

"0196","00000000","00"

"0197","00000000","00"

"0198","00000000","00"

"0199","00100010","22"

"019A","00000000","00"

"019B","00010001","11"

"019C","00000000","00"

"019D","00000000","00"

"019E","00100010","22"

"019F","00000000","00"

"01A0","00010001","11"

"01A1","00000000","00"

"01A2","00000000","00"

"01A3","00000000","00"

"01E0","00000001","01"

"01E1","00000010","02"

"0230","00000000","00"

"0231","00000000","00"

"0232","00000001","00"

and then to cal VCO I do

"0018","00000110","06"

0232","00000000","00"

"0018","00000111","07"

0232","00000001","00"

Please help me!!!!

BR

Orlando

  • 0
    •  Analog Employees 
    on Apr 6, 2016 7:15 PM over 4 years ago

    Hi Orlando,

    The first thing that jumps out at me is that there is a slight error in your calibration sequence:

    Current sequence:

    "0018","00000110","06"

    0232","00000000","00"

    "0018","00000111","07"

    0232","00000001","00"

     

    Adjusted sequence:

    "0018","00000110","06"

    0232","00000001","01"

    "0018","00000111","07"

    0232","00000001","01"

     

    Also please ensure that you have the REF_SEL pin set low to force the PLL to use REF1 rather than REF2.

     

    Typically, if the PLL has not locked and it is set as the source of the distribution dividers, the dividers will be held in reset until locked is achieved, which would explain why you are not seeing an output in this mode. If the VCO is not the source to the dividers, this sync source is bypassed.

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:25 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin