AD9578 questions

I am considering using this device in a measurement instrument which relies upon very low phase drift between two clocks. The AD9578 has two outputs driven from each PLL. With this arrangement one would expect any low frequency drift or jitter from the PLL to be common mode between the two outputs, even when the dividers are set to different values. However the data sheet specifies an offset skew between the two outputs. What is the origin of this? What is the expected temperature variation and long term stability of this skew? ( I will be using LVPECL mode).

  This skew is stated to be independent of the divide value. Does this mean the output dividers are fully synchronous?

Why is the skew specified for positive going outputs ( with a differential output this does not make sense)?

I would like to wire OR two of the outputs , say output2 and output3, both set to LVPECL, so I can switch between two frequencies using the enable bits. The data sheet states that unused outputs are high impedance. Can you confirm that the wired OR arrangement will work?


Cosmo Little

  • Hi Cosmo Little,

    You are correct, OUT 1 & 2 are clocked by PLL1 and OUT 2 & 3 are clocked by PLL2.   OUT 1 and 2 will have "common" jitter and wander and track one another.   They are synchronous dividers.   Skew is specified for rising edge, just to be specific about how to measure it.   Nonetheless, both edges are equally valid in this regard.   Skew exists at all because everything from transistor mismatch to different package parasitics induce very small differences in output delay; but the outputs will remain frequency locked as you indicate, since they share the same input clock.

    You may wire OR the LVPECL outputs.   Please note page 22 of the datasheet; the outputs have specific delays on both turn on and turn off to ensure there are no "glitches".   As long as these delays do not harm your timing design, it is perfectly OK to wire-or the outputs.

    A disabled output does go high Z, but there is a short delay, measured in microseconds, for it to do so.   After this delay, a disabled output is high Z.   Even before the delay however, there is no problem with wire-OR'd outputs in LVPECL mode.


    Steve Beccue

    Analog Devices AD9578 engineer.

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    •  Analog Employees 
    on Aug 2, 2018 3:26 PM
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