ADCLK925 sine wave input

Hi!

Can I connect to input of ADCLK925  sine wave signal with level +22 dBm and frequency 800 MHz?

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  • The AD9528 is a perfectly nice PLL, but it's not a source. That's because as a PLL its output noise is dependent, at least at low offset frequencies, to the noise of the reference (and in this case also the VCO) that the user provides. As a comparison, the integrated noise of the AD9528 (creating a 122 MHz clock) from 12 kHz to 20 MHz (Figure 14 of its data sheet) is 158 fs. Over the same integration range the noise of the "cheap" Wenzel ONYX is about 28 fs, while the expensive Citrine is 6 fs (both at 100 MHz output). It's not a fair comparison because the AD9528 is not an OCXO, and the OCXO's are not PLL's. They each do things the other can't, but as far as ultra-low noise outputs go (about the only thing an OCXO really does), it's hard to beat a good OCXO - and that's why they get the big bucks.

    But back to the original point: For the ADCLK925, how do you avoid the nasty region of noise (slew rates under 1 V/ns) in Figure 12, if you're stuck with a fairly low frequency (100 MHz) sine-wave source?

    One solution is crank the amplitude. But if you're saying the most that can safely be used is 3.4 Vpp (14.6 dBm) then for a 100 MHz signal the slew rate is 1.07 V/ns - which, according to Figure 12, will still produce about 100 fs of added noise. It's a tough problem. I'll play with it and see....

  • 0
    •  Analog Employees 
    on Dec 14, 2018 8:32 PM over 2 years ago in reply to tonyr

    Hi tonyr,

    you are right about AD9528 noise and your jitter targets.

    Here, people are of opinion that you should also try using a comparator to transform the sinusoid into a square waveform. But you need to look into the noise contribution of that comparator.

    Best regards

    Petre

  • VCO Alone

    VCO->ADCLk925->ADCLK946

    Hi Guys,

    I thought about a comparator, because that would certainly increase the slew rate, but, as you mention, comparators are not noise free devices.

    In the mean time we had the opportunity to measure the noise contribution of a ADCLK925 -> ADCLK946 signal chain on the jitter of a not-so-great VCO at 100 MHz. The circuit is: 100 MHz VCO with a +10 dBm sinewave output goes into a SMA connected to a ADCLK925 (single ended), that output goes into a ADCLK946 (differential), and then one of the ADCLK946 outputs is terminated into 50 ohms and goes to a SMA connector ... then through a cable and into our HP/Agilent/Keysight/You-Guess-Their-Next-Name E5052B Signal Source Analyzer.

    The VCO alone has an integrated noise [10 Hz, 10 MHz] of 234 fs (see attachment above?), which is junk, but that's all we have in our lab right now. The output of the ADCLK925-946 chain has an integrated noise [10 Hz, 10 MHz] of 279 fs (see attachment above?).

    The analysis is as follows:

    The added noise should be a calculable quantity from the added jitter plots of the ADCLK925 (Figure 12) and ADCLK946 (also Figure 12). The ADCLK925 output slew rate is approximately 600 mV in 100 ps (from Figure 10) which makes for a slew rate of 6 V/ns. From Figure 12 of the ADCLK946 datasheet that would correspond to an added jitter of about 85 fs in the ADCLK946.

    The added jitter of the ADCLK925 can be approximated from Figure 12. For a 100 MHz +10.2 dBm signal (VCO) the slew rate is 0.64 V/ns, corresponding to ~160 fs added jitter.

     The input jitter of the VCO is 234 fs, so the output should be about 296 fs = SQRT(234^2 + 85^2 + 160^2). The measured number is 279 fs which is reasonably close - but not quite on the money, something else is at play.

    Anyway, at least now we have some data which more or less confirms our suspicion that for a low slew rate input the ADCLK925 is not what you want for clock distribution if you're paranoid about noise. In February, Santa promised to bring us the $2700 Wenzel Citrine Gold 100 MHz OCXO (Santa might be a  nerd, but hey, he's not cheap), and we'll measure the chain again. We'll have to lower the OCXO output to 14 dBm (without using an attenuator) and then the data will show just the ADCLK925-946 combo. That, I hope, will be more conclusive.

    One note to you guys at AD: Look at the noise plot of the ADCLK946 (Figure 11). Now look at the noise plot of the ADCLK948 (also Figure 11). See a resemblance? More than a resemblance, in fact I'd say they're the exact same plot. The ADCLK946 and 948 are similar, but not identical devices (the ADCLK948 has a very nice useful MUX in the signal path), so it's impossible that they have the exact same identical noise output. This plot corresponds to one of the devices (but not both), which one? And guys, come on, don't be lazy, measure both.

  • 0
    •  Analog Employees 
    on Dec 20, 2018 2:01 PM over 2 years ago in reply to tonyr

    Hi tonyr,

    The E5052B RF IN port is already a 50ohm. So there is no need to terminate the ADCLK946 into a 50ohm and then plug that into the E5052B. You just lowered the load impedance for the ADCLK946 driver and the voltage of the clock signal seen by E5052B is in half. So the measured noise is greater than would have been otherwise.

    Then, please note that the jitter function of slew rate plots are typical plots and the rms jitter characteristic when the slew rate is small is very harsh, so the jitter value you extract is only an approximation. These approximations may be the reason why you obtain a difference between the measured value and your computations.

    Regarding your comment about ADCLK948 (released to sales in July 2009) and ADCLK946 (released to sales in April 2009) having the same phase noise plot: Yes, the mux in the ADCLK948 can be considered as introducing some additional noise because it is in the data path of the ADCLK948 and it's not in the ADCLK946. I suppose the same plot from ADCLK946 data sheet was used in the ADCLK948 data sheet to show there was no degradation in performance between the chips.

    Petre