Can I connect to input of ADCLK925 sine wave signal with level +22 dBm and frequency 800 MHz?
Does the 3.4Vpp limit apply to an AC coupled (single-ended) input to the ADCLK925? I've overdriven ADC clock inputs (that were AC coupled) with no smoke coming from the device - but a visible improvement in the noise level.
The purpose here is to get away from the region, in Figure 12 of the datasheet, where slew rates under 1 V/ns induce substantial jitter.
For example a very clean 100 MHz OCXO (say a Wenzel ONYX IV series ~$400) with a sinewave output of +10 dBm (2Vpp) has zero-crossing peak slew rate of 0.63 V/ns. From Figure 12 that would correspond to about 175 fs added jitter - completely trashing the OCXO's low noise output (36 fs [10 Hz, 10 MHz].
However, if the 100 MHz OCXO has a +18 dBm (5Vpp) output (like from a exceptionally low noise Wenzel Citrine Gold - $2700), then the zero-crossing slew rate is now 1.6 V/ns which, from Figure 12, should only produce 90 fs added jitter - which still swamps the OCXO's output noise (13 fs [10 Hz, 10 MHz]) - but it's better.
The clock inputs D and DB of the ADCLK925 accept ac coupled differential signals. See figure 28 in the data sheet:
So the input differential range of 0.2V to 3.4 Vp-p applies.
Instead of buying such expensive OCXOs to create a clean clock, maybe you can use the a clock generator like AD9528 (look at the selection table here for more choices: https://www.analog.com/en/parametricsearch/10732)
to generate a clean 100MHz from a cheaper OCXO.