I am trying to develop a spread sheet to calculate the A,B,C and D coefficients that set the frequency in rational mode. This has shown up some anomalies involving the use of the phase interpolation B coefficient ( S = 0,1,2):

Generally there are a number of different internal divider values that may be used to generate a particular output frequency, keeping the VCO frequency within the limits. For each of these cases, there will be a feedback divider consisting of an integer divider and a fractional divider. Coefficient A is the integer divider.

The fractional divider may be evaluated using up to 15 different combinations of the B,C, and D coefficients.

For some of these, the ratio C/D may be greater than 1, and still result in a fractional divider that is less than 1. For example,S=0, C/D=1.504, B=6 gives a fractional divider of 0.938.

Is this a valid mode of operation?

For some combinations of B,C, and D, the fractional divider may be greater than 1. For example, S=0, C/D=2,B=7 gives a fractional divider of 1.125.

Is this a valid mode of operation?

Once the valid ratios C/D have been calculated as a decimal, these are then converted to an irreducible fraction to give the individual values for C and D. Some of these fractions have substantially smaller integers in numerator and denominator than others.

What is the effect on phase noise and spurii of using different irreducible fractions?

As the C and D registers have 16 bits each, is there any advantage in reducing the C/D ratio at all?

Are there any application notes or technical papers relating to the operation of the AD9578 in rational mode?

regards

Cosmo Little