AD9578 problem

At last I have finished my own development PCB and  software to program the AD9578 in rational mode. I can enter the frequency , and the software finds the minimum fractional divider,  minimum modulus, and output divider to generate the desired frequency. I can also read back the registers. I am currently using output1 and output2, both driven from PLL1. The outputs are set to LVPECL mode.

    Everything works, except that occasionally the output disappears from both outputs, and a power on reset is needed to restore normal function. Reading back the registers after this strange failure shows all the registers unchanged, with PLL1 still showing locked. The outputs are still LVPECL, with correct DC levels, however there is no AC output.

     The fault occurs from a few seconds to many minutes after power on reset and programming. After the failure, re-programming the registers has no effect.

    I am fairly sure that the power supplies are OK, with no glitches. If the chip was resetting, I would expect the registers to go back to the default, which they do not. When I program the chip, I first write to register2 with the MR bit set. I then write the correct data to register2 with the MR bit cleared. I then program all the other registers in order except registers 10,11,and 13. The following is the register data, starting with register1. note 32 bit registers have 2 trailing zeros, and 24bit registers 4 trailing zeros, etc.


The frequency is 39.96MHz, the fractional divider is 117, the modulus 125, the integer divider 63, and the output dividers 80.

S is 3.

I hope you can advise on this problem

best regards

Cosmo Little

  • Further to my post, this problem is related to some form of power supply glitch, as switching other equipment on and off causes it. I am now concerned that the problem cannot be monitored by reading the lock bits, as these are unchanged after the failure.

  • Cosmo,

    I discussed this with another engineer, and the odds are that power glitches are the issue here.   It is quite possible to have a power glitch that does not knock the PLL out of lock.   The VDDO power and VDD power are seperate.  So please check the output enable bits to see if the outputs are disabled.    It sounds a little like the output goes away?   An unlocked pll would still have output, just the wrong frequency and jittery.   An internal loss of "enable" will turn off outputs.   The later is powered by the VDDO supply, and the former by the VDD supply.   Please check the OE bits and quality of the VDDO.



  • Dear Steve,

    The stuck state is definitely triggered by some sort of power supply glitch, as switching on line powered  test equipment triggers it. I have checked various things as you suggested:

    1/- The outputs ( 1 and 2) are definitely still enabled. The output voltages on the differential outputs are the normal LVPECL levels, ie 2.0 volts on one output and 2.4V on the other.

    2/- There is no apparent change in supply current on entry to the stuck state.

    3/- The output enable pin override bits are all set in the programming.

    The board is powered from a lab power supply. There is a switched mode 6.3V  regulator on the board, and each supply has an individual 3.3V linear regulator. The AD9578 Vdd pin is powered from the main digital Vdd (3.3V) . The Ad9578 

    VddA pins are all connected together to a power plane  which has an individual 3.3V regulator. The AD9578 ground pad is connected directly to the main digital ground plane. Each output has an individual ground plane and 3.3V regulator, using the individual VssO and VddO pins provided.

    I have attached a part schematic. 

    What is the " activity detector" ? 

    The individual ground planes are all tied together at one point. I can measure a few mV difference in DC level between the ground pins at the chip ( ground pad to VssO1,VssO2/3, and VssO4)  It is possible that there may be AC transients between the grounds, but these cannot be more than a few mV.

    I am quite concerned that this stuck state exists at all, and is not self correcting, as it is apparently impossible for the processor to detect it.

    I hope you can help further.


    Cosmo Little

  • Dear Steve,

      I have now made further measurements of the signal levels between the output grounds ( pins 1, 9/27, and 35) and the main chip ground (pins 10,36,and ground pad) . Note that pins 10 and 36 are tied directly to the ground pad, which is connected to the digital ground plane with multiple vias. The 3 separate output grounds are connected to individual ground planes. The individual voltage regulators are referenced to each output ground plane , and supply each output. This should be clear from the schematic. The individual output ground planes are connected to the main analog ground plane at different points. The analog ground plane is connected to the digital ground plane at one point.

      The objective of this arrangement is to take advantage of the individual ground and power pins for each of the outputs, to reduce digitally generated spurii on the outputs.


      I have measured ( using an oscilloscope 1/10 probe with a spanner ground)  between 100 and 200 mV PtoP between the main chip ground and each of the output grounds. These measurements were made as close to the chip as possible. The frequency was entirely at the reference frequency ( 50MHz), however with a large third harmonic component. Measurements with a spectrum analyser with a 500ohm probe confirmed that the levels as -16dBm ( 50MHz), -25dBm(100MHz) and -13dBm (150MHz)

    It seemed possible that I was over driving the reference input. I measured  the 50MHz reference directly on the X02 pin.

    The voltage range was -0.2V to 2.2V. The input capacitance of the probe was probably reducing the level slightly. The data sheet is not clear as to the maximum levels for AC coupled inputs.

    To conclude, the chip must be driving substantial ground currents into the output ground planes to give such a high signal level. I guess that the inductive path between the output grounds and the main chip ground via the ground planes must be less than 100nH. This would give peak currents around 3mA.

    The chip must be very close to the point of entering the stuck state on its own, and the slightest spike on the output ground planes will trigger this. Could this be caused by excessive reference signal?

    best regards

    Cosmo Little

  • Cosmo,

    I agree you found the problem.   That amount of voltage between VSSs is going to be a problem.   It could become destructive if it hits 0.6V, even with a very narrow spike.

    Do you really mean 100nh?   Seems very high.

    The VSSs should be tied together at one point, as you indicate, ideally underneath or very near the AD9578.    Is the connection far from the IC?   Very, very narrow?    Hundreds of mV seems much too high.

    In the short run, as a debug test, can you apply (dead bug fashion) ground wires between VSSs and see if the problem is reduced or eliminated?

    WRT reference drive:  How do you have the line terminated?   (The refin inputs provide a lower capacitance input than XO2.)    The XO inputs, though usable, were really intended for quartz, while the refin were designed for external references.     Please reduce the input power if you are finding reference spurs.   However, if ground becomes much lower impedance, you may find that issue goes away.

    Activity detect just is a check on the output dividers to see they are functioning.   You should not have to change this bit.