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Clock and Timing

Q&A ADN2913

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ADN2913

hnl on Nov 7, 2016

How does ADN2812 jitter could not tolerate 0.067 UIp-p synchronizing with 15 MHZ data stream; could ADN2913 tolerate the 0.067 UIp-p at 15MHZ?

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on Nov 8, 2016 12:02 AM
Dear HNL,

Sorry for my typo, it should be 1.3MHz instead of 1.3kHz.

Did you lock on to an input clock signal or a burst mode PRBS type of modulated data signals?

Both ADN2812 and ADN2913 supports continuous mode, PRBS type, NRZ encoded data signals. If your input data signal is a burst mode signal, both ADN2812 and ADN2913 would lost lock easily.

Best Regards,

Dongfeng
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0 ADIApproved

on Nov 8, 2016 12:02 AM
Dear HNL,

Sorry for my typo, it should be 1.3MHz instead of 1.3kHz.

Did you lock on to an input clock signal or a burst mode PRBS type of modulated data signals?

Both ADN2812 and ADN2913 supports continuous mode, PRBS type, NRZ encoded data signals. If your input data signal is a burst mode signal, both ADN2812 and ADN2913 would lost lock easily.

Best Regards,

Dongfeng
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