Need a ADI recommended Fractional N PLL

Question

Hello, 
 My customer wants to use ADI PLL devices, so they request your recommeded PLL device adapting below conditions. 
 Please refer below conditions and let me know your opinions. 
 Case 1: 
 1. Reference Frequency: 153.6MHz 
 2. Reference Frequency: 10MHz 
 3. Output Clock Frequency: 322.265625MHz 
 
 If you can recommend, both reference Frequencies are supported. 
 If you can't, 153.6MHz is more important than 10MHz. 
 Would you recommend ADI PLL adapting above conditions? 
 Case 2: 
 1. Reference Frequency: 322.265625MHz 
 2. Output Clock Frequency: 153.6MHz 
 
 If 322.265625MHz is too high, they can use divided- N (integer) frequency of this. 
 
 Would you recommend ADI PLL adapting above conditions? 
 Please advise me. 
 Regards, 
 Se-woong

neilw · Accepted Answer

Hi Se-woong, 
 This really comes down to the application for which the device is intended to be used. The products you listed are great RF synthesizer products that offer great noise performance. These synthesizers are typically used when you have a dedicated, reliable reference clock and you need to up-convert it to a very clean sampling clock. 
 The AD9557 is a clock/synchronizer product that offers features such as reference monitoring, phase build-out switching, jitter clean up (down to 0.1 Hz loop bandwidth operation) of the reference input clocks, and holdover operation. It is typically used to create a dedicated, reliable reference clock that insulates down stream devices from system events (i.e. change of synchronization reference, filtering excess upstream jitter, etc.) 
 I must profess that my knowledge of the particulars of the HMC RF PLLs is somewhat limited, but operating at a 25 kHz PFD rate to achieve this frequency translation seems to imply to me that ADIsimPLL is configuring the N divider into integer mode. The low PFD frequency will elevate the PLL's pedestal and it may degrade the phase noise performance enough that you my want to operate in fractional-N mode with a higher PFD frequency. 16-bits of fraction is enough to make your translation for both case #1 and case #2.

neilw · Answer

Hi Se-woong, 
 I would recommend the AD9557 product. It is a two input two output any-rate translator DPLL that can handle each case as specified above.

neilw · Answer

Hi Se-woong, 
 The AD9557's system clock input must be a dependable signal. There is no tolerance for it to disappear or experience transients (beyond typical aging/temperature variations of a free-running oscillator). 
 While technically the system clock and reference clock could be the same, I cannot think of a single scenario where this would be recommended versus just operating the AD9957 in free-run. It is firmly not recommended. 
 Typically, a dedicated XTAL is used as the system clock input source. If this is unacceptable for your application, the AD9552 (supports only a single reference frequency and must divide down reference below 100 MHz) and the AD9576 (supports only a single reference frequency and must divide down reference below 320 MHz) can also do the frequency translations requested in the two specified cases.

ADIApproved · Answer

Hi Se-woong 
 The HMC703, HMC704 and HMC7759 are all PLL devices -- you will need a VCO running at your desired RF frequency. Both HMC703 and HMC704 offer comparable performance. Use the HMC703 if you need to sweep or modulate the VCO output. The HMC7759 is not released yet. 
 
 The other devices mentioned in your list are all PLLVCO devices which meet your requirement. Our best performing part, in terms of phase noise and spurious, is the HMC830. This part requires 3.3V and 5V rails. Use the HMC832 or HMC832A if your application requires a single 3.3V rail (the "A" variant supports 1.8V logic). The phase detector in all these devices can run up to 100MHz -- as Neil mentioned operating the PFD at a low comparison frequency just degrades performance. 
 The HMC833 is exactly the HMC830 but with output doubler to extend the frequency range to 6GHz. 
 The HMC834 is a variant of the HMC829 but with doubler. 
 The HMC835 provides two differential RF outputs and two charge pump outputs. This device has phase alignment capability.

Electronic Design Services - PartnerZone

Need a ADI recommended Fractional N PLL

Top Replies