I have a clock input (50 ohm single-ended from SMA) that will be in the range of 10MHz to about 3GHz. I'd like to buffer that clock using the ADCLK905 before routing to a PLL IC.
My question is: is there an advantage to balun-coupling this input vs simply using a coupling capacitor with the recommended single-ended termination in the datasheet? Is there an obvious choice between the two options?
I can make the voltage ranges work regardless of the topology, but I'd like to know if I'm going to get bit AC-coupling a 3GHz clock into the ADCLK905 using the cap only (would prefer this to save space vs a balun).