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ADN2812 CDR

=== ADN2812 CDR ===

The LOL (loss of lock) of ADN2812 is asserted around every 200ms for short  period in our system.

The datasheet shows it will return frequency acquisition mode when frequency difference between VCO & incoming data over 1000 ppm. The LOL is asserted in frequency acquisition mode.

Suppose the jitter of our system is over 1000ppm sometimes, and under 1000ppm at most of time.

Is it possible to extend the criteria to return frequency acquisition mode from 1000ppm to 2000ppm, 5000ppm. Or something likes that. Thanks.

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  • Hi Dongfeng,

    Thanks for your reply.

    1. What is the input signal data rate in your applications?  --> 300Mbps ~ 1Gbps. 400Mbps in current testing.
    2. What is the applications you use this ADN2812 as the signal CDR? --> an proprietary protocol.
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode? --> Lock to Data.
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?  --> We don't have the EVB.

    From Fig1, the LOL is asserted around every 200ms. I am still cooking the reason.

    From Fig2, the output clock is reset to a lower one when LOL is asserted.

    Because the CRC is embedded in the protocol, the receiver can detect if the data received correct or not.

    We think the error period should be small compared to the re-lock time.

    Is it possible to release the error threshold for re-lock from 1000ppm to 2000ppm or more?

    Then we can lose less data during these error period.

    Thanks a lot.

    Fig1

    Fig2

Reply
  • Hi Dongfeng,

    Thanks for your reply.

    1. What is the input signal data rate in your applications?  --> 300Mbps ~ 1Gbps. 400Mbps in current testing.
    2. What is the applications you use this ADN2812 as the signal CDR? --> an proprietary protocol.
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode? --> Lock to Data.
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?  --> We don't have the EVB.

    From Fig1, the LOL is asserted around every 200ms. I am still cooking the reason.

    From Fig2, the output clock is reset to a lower one when LOL is asserted.

    Because the CRC is embedded in the protocol, the receiver can detect if the data received correct or not.

    We think the error period should be small compared to the re-lock time.

    Is it possible to release the error threshold for re-lock from 1000ppm to 2000ppm or more?

    Then we can lose less data during these error period.

    Thanks a lot.

    Fig1

    Fig2

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