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ADN2812 CDR

=== ADN2812 CDR ===

The LOL (loss of lock) of ADN2812 is asserted around every 200ms for short  period in our system.

The datasheet shows it will return frequency acquisition mode when frequency difference between VCO & incoming data over 1000 ppm. The LOL is asserted in frequency acquisition mode.

Suppose the jitter of our system is over 1000ppm sometimes, and under 1000ppm at most of time.

Is it possible to extend the criteria to return frequency acquisition mode from 1000ppm to 2000ppm, 5000ppm. Or something likes that. Thanks.

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  • Dear Gavinwang,

     

    ADN2812 is designed to be GR-253 core compliant. Any input signal with worse jitter than those specified in GR-253 core could send ADN2812 into loss of lock state.

     

    In the CDR LOL state, the LOL pin would output a toggle signal, meaning CDR tries to adjust its VCO to mate the input signal frequency but fails to do so, then repeat the input frequency acquisition…

     

    So, you might need to check your system input signal quality first, don't abuse ADN2812 as an "any garbage signal cleaner".

     

    To use the ADN2812 properly, may we know:

    1. What is the input signal data rate in your applications?
    2. What is the applications you use this ADN2812 as the signal CDR?
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode?
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?

     

    Best Regards,

     

    Dongfeng

Reply
  • Dear Gavinwang,

     

    ADN2812 is designed to be GR-253 core compliant. Any input signal with worse jitter than those specified in GR-253 core could send ADN2812 into loss of lock state.

     

    In the CDR LOL state, the LOL pin would output a toggle signal, meaning CDR tries to adjust its VCO to mate the input signal frequency but fails to do so, then repeat the input frequency acquisition…

     

    So, you might need to check your system input signal quality first, don't abuse ADN2812 as an "any garbage signal cleaner".

     

    To use the ADN2812 properly, may we know:

    1. What is the input signal data rate in your applications?
    2. What is the applications you use this ADN2812 as the signal CDR?
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode?
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?

     

    Best Regards,

     

    Dongfeng

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