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ADN2812 CDR

=== ADN2812 CDR ===

The LOL (loss of lock) of ADN2812 is asserted around every 200ms for short  period in our system.

The datasheet shows it will return frequency acquisition mode when frequency difference between VCO & incoming data over 1000 ppm. The LOL is asserted in frequency acquisition mode.

Suppose the jitter of our system is over 1000ppm sometimes, and under 1000ppm at most of time.

Is it possible to extend the criteria to return frequency acquisition mode from 1000ppm to 2000ppm, 5000ppm. Or something likes that. Thanks.

  • Dear Gavinwang,

     

    ADN2812 is designed to be GR-253 core compliant. Any input signal with worse jitter than those specified in GR-253 core could send ADN2812 into loss of lock state.

     

    In the CDR LOL state, the LOL pin would output a toggle signal, meaning CDR tries to adjust its VCO to mate the input signal frequency but fails to do so, then repeat the input frequency acquisition…

     

    So, you might need to check your system input signal quality first, don't abuse ADN2812 as an "any garbage signal cleaner".

     

    To use the ADN2812 properly, may we know:

    1. What is the input signal data rate in your applications?
    2. What is the applications you use this ADN2812 as the signal CDR?
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode?
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?

     

    Best Regards,

     

    Dongfeng

  • Hi Dongfeng,

    Thanks for your reply.

    1. What is the input signal data rate in your applications?  --> 300Mbps ~ 1Gbps. 400Mbps in current testing.
    2. What is the applications you use this ADN2812 as the signal CDR? --> an proprietary protocol.
    3. What is the CDR working mode when you see the LOL, is it in LTD or LTR mode? --> Lock to Data.
    4. Could you duplicate the same LOL behavior by using one EVAL-ADN2812EBZ board?  --> We don't have the EVB.

    From Fig1, the LOL is asserted around every 200ms. I am still cooking the reason.

    From Fig2, the output clock is reset to a lower one when LOL is asserted.

    Because the CRC is embedded in the protocol, the receiver can detect if the data received correct or not.

    We think the error period should be small compared to the re-lock time.

    Is it possible to release the error threshold for re-lock from 1000ppm to 2000ppm or more?

    Then we can lose less data during these error period.

    Thanks a lot.

    Fig1

    Fig2

  • Dear Gavinwang,

    Thank you for your replies.

    Now, let me understand

    1.   What is the input signal scheme, a PRBS 31 signal in NRZ encoding?  If not, please elaborate your input signal;

    2.   how you connect your input signal to the ADN2812, through DC interface or a AC coupled interface?

    3.   Is this input signal in a continuous mode or pulse mode? Pulse mode means even the signal is at 400Mbps, but it has a lower pulse modulated together.

    the pulsed signal turns on or off the 400Mbps signal.

    My concern is, your input signal might be something else rather than a  required continuous mode, 400Mbps signal, in PRBS 7 or 31, encoded in NRZ.

    In general, if your input signal is a pulsed signal, ADN2812 would easily see LOL toggles, and no lock to the input signal.

    Please confirm what input signal you applied to the ADN2812.

    Best Regards,

    Dongfeng

  • Hi Dongfeng,

    Thanks for your reply.

    1. The signal is normal pattern in NRZ encoding. Not by PRBS7 test pattern.

    2. by AC-coupling.

    3. The signal is continuous type. But there exist some long "1" or long "0" pattern. The longest run is 11.

    Please check "D2" in Fig1. of previous post. The pattern is repeated every "D2" toggle, named as one frame(around 16.7ms). So the LOL is asserted around every 12 frames(around 200ms).

    Is it possible to release the re-lock threshold from 1000ppm to more?

    Thanks a lot.

  • Dear Gavin,

    Long time no see you. Is this issue still open?

    Unfortunately, we have no way to extend the CDR lock-in Hysteresis by programming registers. Everything is fixed by the ADN2812 IC design.

    Best Regards,

    Dongfeng

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