AD9578 problem

Dear Steve,

I now have a lot of experience with the AD9578, however I have a programming problem:

The device sometimes fails to lock properly ( unstable frequency a few kHz low) after repeating a programming sequence with the same values. The sequence I use  is:

1/- toggle MR bit

2/- program all registers

3/- read and print all registers

The device is now locked and outputting the correct frequency

Now repeat the above sequence with exactly the same register values

The device is now in the unstable lock mode

The read back of the registers gives identical values.

Repeating the sequence always gives an incorrect lock.

This problem occurs both in rational and fractional modes.

After the master reset, should the device be in exactly the same default  state?

Note that programming after a power on reset gives a correct lock. Also programming a completely new frequency sometimes resets the stuck mode.

best regards

Cosmo Little

  • A MR is not the same as a power up condition.   The difference is the OTP bits are not reload.   (You are not writing the reserved registers, correct?   They may differ from part to part).    You MUST issue fbdiv_resets after changing registers, so just rewriting the registers in order will not work.   The numbers will read back correctly, but the fbdiv is required after the fb_div values have been changed.    Please try this and let me know if the issue is resolved.

    Regards,

    Steve

  • DEar Steve,

    I have changed the programming so I toggle the “reset feedback divider” bit in registers 7 and 9 after I have programmed all the registers.

    This has had no effect on the problem.

    The first programming after a power on reset is correct.

    If I then repeat the programming, the lock is incorrect.

    The parameters are:    output divider: 5

                                        integer divider: 64

                                        fractional divider: 839

                                        modulus            : 2500

                                        ref freq               : 50MHz

                                        VCO freq            : 3216.78MHz

                                        Output freq        : 643.356MHz

    The actual output frequency when the lock is incorrect is:  643.40314MHz. A spectrum analyser shows this to have very high close in phase noise.

    In all cases the registers read back correctly: (leading zeros suppressed)

          7A0800000000    reg1

                       5775F

                 10050000

                            AA

                    505005

            400068E04E

             6473700427

           3F000EA3DE

             6474700401

                              0

               26AAAAA2

               83AAAAAA

             26AAAAA2

                 3AAAAAA

                    A60000    reg15

    PLL2 is correctly locked, and both PLL show as locked in reg 15.

    I am now quite concerned about this problem.

    best regards

    Cosmo little

  • Dear Steve,

    Some more information on the problem:

    1/- There is no problem if only PLL1 is used, with the frequency set to 643.356MHz. Any number of register programmings gives the correct lock.

    2/- If both PLL are in use, on different frequencies, I get the problem:

    PLL1    programmed to 39.96MHz        actual frequency  39.962952MHZ    incorrect lock

    PLL2    programmed to 643.356MHz    actual frequency  643.356MHz        correct lock

    OR

    PLL1    programmed to 643.356MHz   actual frequency  643.403112MHz  incorrect lock

    PLL2    programmed to 39.96MHz        actual frequency 39.96MHz            correct lock.

    Can there be some sort of interaction between the two PLL?

    It seems that the problem is with PLL1 not PLL2.

    regards

    Cosmo Little

  • Dear Steve,

      I have now added a test mode to my software to force the AD9578 to always use both PLL, even when the two required output frequencies are the same. ( Normally it tries to use one PLL with the same or different output dividers)

    I have found that after programming 643.560MHz  to both PLL , PLL2 always locks correctly, but PLL1 does not.

    I can see from the registers that the programming of both PLL is identical.

    PLL1 locks OK provided PLL2 is off. Whenever PLL2 is on, PLL1 gets permanently stuck in a state where it does not lock.

    This is all very strange, perhaps it is a hardware fault?

    regards

    Cosmo Little