ADIsimCLK ver1.7 bug? @AD9520-x

1.AD9520-5 model
Can not it simulate the PLL with external VCO ?
Is it bug ?

Yes, this is a bug. Thanks for finding it. As a workaround you should be able to design loop filters and predict phase noise / jitter using the AD9520-4 (as it looks like you have tried).

2.AD9520-4 model
It can simulate the PLL with external VCO, but can not change the R divider.
Is it bug ?

How to simulate the PLL with external VCO @ AD9520-4, changing the R divider ?

When you set up the design using the wizard pages, you set the PD frequency here:

and the reference frequency on a later page:

if you change the reference frequency here, R will change.

To revisit the wizard pages, click on the configuration button from the main toolbar.

1.AD9520-5 model
Can not it simulate the PLL with external VCO ?
Is it bug ?

Yes, this is a bug. Thanks for finding it. As a workaround you should be able to design loop filters and predict phase noise / jitter using the AD9520-4 (as it looks like you have tried).

2.AD9520-4 model
It can simulate the PLL with external VCO, but can not change the R divider.
Is it bug ?

How to simulate the PLL with external VCO @ AD9520-4, changing the R divider ?

When you set up the design using the wizard pages, you set the PD frequency here:

and the reference frequency on a later page:

if you change the reference frequency here, R will change.

To revisit the wizard pages, click on the configuration button from the main toolbar.