AD9558 does not lock on LVDS reference clocks

Hi,

We use an AD9558 and have two different differential reference clocks and none of it is accepted as a valid clock. What could possibly be wrong?

REFC is 10 MHz, dc-coupled, with 100 Ohm termination on the AD9558 side, directly driven by an LVDS clock buffer.

REFD is 125 MHz, ac-coupled, with 100 Ohm termination on the AD9558 side, driven by an FPGA (LVDS).

Both LVDS references (C and D) look fine on an oscilloscope.

REFA and REFB are driven by LVCMOS sources and are accepted as valid clocks. The PLL configuration was generated using Analog's AD9558 Evaluation Software.

Thank you in advance.

Kind Regards,

 Chris

  • Hello Chris,

    Have you selected differential mode for REFC and REFD? To do so, ensure that Register 0x0601<7:4> are all zeros.

    Also, you can tell if the input is in differential mode on REFD by verifying that the (internally generated) common mode voltage is about 2V on the AD9558 side of the decoupling caps.

    The other possibilities (if you're not reading REFC/D valid) is that the input frequency is out of tolerance.

    If REFC/D are valid, but they're not being used, it could be that they don't have priority any higher than REFA/B, and the AD9558 will not switch to REFC/D if REFA/B are the same priority and already being used.

    -Paul Kern