EVAL-AD9557 for generating clock signal that matches varying input frequency?

Greetings!

To provide some contextual background, I'm looking for a solution to generate clock multiples of the fs laser pulse rate, which can be something close to 80  MHz, in my case 80.11 MHz. During laser operation this frequency constantly changes by less than 100 ppm at the rate of ~ 15 Hz. I was recommended AD9557 for the job

AD9523-1  Can I precisely adjust output clock frequency with AD9523-1 (EVAL-AD9523-1)? 

I just would like to follow up and confirm if AD9557 is going to "follow" this small frequency drift with this configuration?

Thank you!

Dmitri

  • 0
    •  Analog Employees 
    on Jul 6, 2017 12:25 AM

    Hi Dmitri,

    Yes. The AD9557 will track the variations on the reference input such that the output is traceable to the input frequency with a ratio of 1:1 for your provided configuration. A few notes:

    1) Set the DPLL feedback divider to 2000 + 0/1 instead of 1999 + 4/4. A frac value that is equal to the modulus is not valid

    2) You have set the DPLL loop bandwidth very high (1 kHz) compared to the 15 Hz variation rate of your input clock. This is just going to cause the DPLL to pass through even more of your reference noise without filtering it which could degrade the phase noise of your output. Though sometimes this tracking is desired, just keep it in mind during your debugging process.

  • Greetings again!

    I seem to have an issue with configuring AD9557 and producing desired frequency output. When I provide 49.152 MHz sine wave as an XOA input, and 20 MHz as Ref A, I observe a clock generation. However, when I try to configure the board  using the desired reference frequency, e.g. 20 or 40 MHz, I see nothing. Could you take a look at these setup files and comment?

  • 0
    •  Analog Employees 
    on Nov 3, 2017 4:19 PM

    Hi dmitrit,

    I sincerely apologize for the delay. My EngineerZone alerts somehow were removed and I am just now seeing this. From your images, the issue seems to be that the APLL has not been re-calibrated since you changed the system clock configuration. You can perform this re-calibration by clicking the VCO icon in the block diagram (see the bottom image in figure 4 in the User Guide for an example).

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:52 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin