Is it possible to input a clock to ADN4670 which has a duty cycle of say 20%. e.g. a 10MHz square wave which has a high time of 20ns? At the outputs of course I require the same duty cycle signal.
In the datasheet Table3: tDUTY is given as 45-55%. Does that mean the inputs and outputs should be in this range?
ADN4670 can be used with a 20% duty cycle clock at 10 MHz (20 ns high time).
The tDUTY specification guarantees that with a 50% duty cycle, the maximum duty cycle distortion will be +/-5%. However, that's even at 900 MHz (0.555 ns high time for 50% duty cycle, 5% distortion is 55.5 ps). So at lower clock rates, duty cycle distortion will be typically much lower, as can be determined by the fact that absolute pulse skew is guaranteed to be less that 50 ps for the tSK(P) specification, i.e. +/-50 ps.
Taking that 50 ps specification, we can expect that the actual output duty cycle with 20% on the input, will be somewhere between 19.95% and 20.05%. In reality, with typical performance, the output duty cycle will even closer to the 20% duty cycle on the input.