In the AD9545 Evaluation board schematic, all the VDD power supply pins are isolated using 0E. Attached is the evaluation board schematic.Please let us know is there any specific reason to isolate individual VDD pins or all of them can be shorted together?
The VDD pins you are asking about can be tied together. The 0 Ohm are there to help investigate any coupling or power supply related issues that may arise during use of the evaluation board. If you have any further power supply related questions, please post them.
I will divide the power supply in different section to decoupling the different parts of the PLL. In the datasheet there isn't a description of the functional attribution at the VDD pins. OK, the VDD pins have the same voltage level and because of the same voltage level the VDD pins can tied together. But the pin placement and the schematic from the eval-board create the guess that nearly each VDD pin stands for a different part of the PLL and most of the VDD pins aren’t internal connected to each other.
E.g. in the schematic from the eval-board are chip beads only at VDD pin 10, 13, 19, 24 and 27. Are they the power supplies of the output buffers at OUT0A, OUT0B, OUT0C, OUT1A and OUT1B? Why are the chip beads between the 100nF and the VDD pins, and not the 100nF between chip beads and VDD pins?
This are my association for the VDD pins:
VDD pin 6 -> APLL0VDD pin 10 -> OUT0AVDD pin 13 -> OUT0BVDD pin 19 -> OUT0CVDD pin 24 -> OUT1BVDD pin 27 -> OUT1AVDD pin 31 -> APLL1VDD pin 40 -> REFBVDD pin 41 -> XO (and maybe SYSTEM CLOCK PLL?)VDD pin 45 -> REFA
For the following VDD pins I haven’t a good association:
VDD pin 9 -> ? (maybe DPLL0)VDD pin 20 -> ? (maybe SYSTEM CLOCK PLL)VDD pin 28 -> ? (maybe DPLL1)
Is there any hardware reverence manual? Please give me further information for the VDD pins and the associations for them.
The beads were put only on the VDD pins that are related to the output drivers because we wanted these outputs to be "isolated" from power supply domain.
The idea behind placing them close to the chip pins and not after the decoupling capacitors is that being in this position cleans both the VDD supply and the ground. Placing the decoupling capacitors near the chip pins and the beats before them cleans only the VDD.
The data sheet does not provide the power domains related to every VDD pin, so I cannot identify them for you. Please use the AD9545 evaluation board schematic as an implementation example because the performance of the chip was verified on this board. Also, always supply all VDD, VDDIOA and VDDIOB pins as the chip was verified with all the pins being supplied.