Questions about PLL design with HMC698LP5

Hello,

My customer are designing PLL circuit  with HMC698LP5 (PLL), HMC391LP4(VCO) and OP27 (OPAMP).

And the ouput frequency are 3.9GHz or 4.05Ghz and the reference frequency is 50MHz.

Q1) when they implement a charge pump  of HMC698, can they implement up/down of charge pump at the same time?

Q2) At this time, can they implement a loop filter circuit as passive type?

Q3) They want to handle a fixed LO as 4.05GHz and 3.9GHz with one OP Amp. (OP27S).

       At this time, can they control a tune voltage with under 1V range through OP27S?

Q4)Would you check below their loop filter design?

.

Please advise me.

Regards,

Se-woong

Parents
  • Hi Se-woong,

    The latest version of ADI SimPLL, 4.30.06 supports all of the products your using and includes the HMC PFD filter. This tool is a bit easier to use than the legacy HMC tool in my opinion.  If you can provide your *.pll file I can import it into the HMC tool and review it for you. The screen shot provided doesn't include other information that would be helpful to know.

    1) The main CP settings for both UP and DN should be enabled otherwise the synthesizer will only achieve lock in one direction.

    2) As far as the VCO is concerned, technically since the frequencies your customer is using fall at 1V a passive loop is possible but would generally not be recommended since the VCO plays to 10V. However, the HMC698 PLL can not be used with a passive loop.

    3) The OP27S like the OP27 does not appear to be a rail-to-rail device so you'll need to apply negative supply bias to allow the output voltage to swing to 1V or less. If you can only provide a positive supply voltage I recommend you consider a low noise, rail-to-rail op amp like the AD8065 or something similar however I'm not sure that this is a rad hard product.

    I attached the ADISimPLL version of your loop filter. Be sure to install the latest version of ADISimPLL or it may not open for you. The loop is set to about 209kHz corner frequency and 67.5 degrees of phase margin. It should be stable over temperature.

    Please reach out to the factory if you need help finding a space qualified linear regulator.

    Best Regards,

    Marty

    EZ_Question_101189_11302017.pll.zip
Reply
  • Hi Se-woong,

    The latest version of ADI SimPLL, 4.30.06 supports all of the products your using and includes the HMC PFD filter. This tool is a bit easier to use than the legacy HMC tool in my opinion.  If you can provide your *.pll file I can import it into the HMC tool and review it for you. The screen shot provided doesn't include other information that would be helpful to know.

    1) The main CP settings for both UP and DN should be enabled otherwise the synthesizer will only achieve lock in one direction.

    2) As far as the VCO is concerned, technically since the frequencies your customer is using fall at 1V a passive loop is possible but would generally not be recommended since the VCO plays to 10V. However, the HMC698 PLL can not be used with a passive loop.

    3) The OP27S like the OP27 does not appear to be a rail-to-rail device so you'll need to apply negative supply bias to allow the output voltage to swing to 1V or less. If you can only provide a positive supply voltage I recommend you consider a low noise, rail-to-rail op amp like the AD8065 or something similar however I'm not sure that this is a rad hard product.

    I attached the ADISimPLL version of your loop filter. Be sure to install the latest version of ADISimPLL or it may not open for you. The loop is set to about 209kHz corner frequency and 67.5 degrees of phase margin. It should be stable over temperature.

    Please reach out to the factory if you need help finding a space qualified linear regulator.

    Best Regards,

    Marty

    EZ_Question_101189_11302017.pll.zip
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