I'm very thankful for your reply. I made the changes as you said and these are the observations.
Fixing the loop BW to 50Hz, I changed the phase and frequency lock thresholds, as well as fill and drain rate. On making the appropriate changes both the lock detectors definitely show green as well as the input is valid and DPLL is "active". I tried changing the gap frequency and size in input and dpll still shows active. Changes in reference monitor and IRQ keep the input valid and DPLL active.
Though all of this is working, the clock is still not tracking the input or it is not seen to be locked with the input on the oscilloscope even though it is ACTIVE mode and lock detectors are on. To make the clock stable and close to locking I have to increase the BW to 1000Hz, which does make it stable, but there is a slight jitter. I have tried variation of very high as well as closer to default values of thresholds and fill rate, which do not effect the input tracking that much.
Since the Active mode means that the input is being tracked, could you think of the reason it is not working. Also, you don't recommend increasing the value of BW, I would be grateful if you could suggest another way.
I am attaching a sample reg map, that shows the register values. I am inputting a 40 MHz periodic waveform, with gaps of one clock in every 200 usec, or 5 KHz.
Be sure to set R0x070E=0x01 to select high phase margin mode. This allows for additional stability at high loop BWs.
Be sure to enable IRQs so that you're 100% sure that the DPLL is always active, that the reference input is always valid, and the the DPLL is always locked. My suspicion is that one of those isn't always true, but that it's toggling so quickly, you're not able to detect it.
Thanks a lot for all the help and advise.
I can see that output locks when REFA is valid and DPLL is active. Although there is still some jitter of about 2-3 ns in the output, which I'm guessing maybe due to the toggling of DPLL or high loop BWs. But I think I can try to decrease the high loop BW and increase the loop threshold values instead.
You had previously mentioned that you have checked gapped clock inputs and it worked fine. Could you tell me what frequency was your input and how frequent was your clock gap, also if you were able to get the input and output to be locked. Because the output of the AD9557 still seems to have fluctuations and jitter, which means it is phase locked for a few period of times only. While the input jitter is in the range of 200ps. The output jitter is around 1 ns for edge jitter which I guess is random jitter so its no that big a problem, while the timing jitter is much higher which is happening as I think the phase lock is fluctuating.