Jitter at output of AD9557 with input of gapped clock (missing pulses) ?

Hi,

 

This is continuing from a previous question about gapped clocks on AD9557 (ad9557 and gapped clock? ), which was replied by .

 

I am currently working on a clock recovery circuit that should output a phase locked clock. The circuit includes a comparator and a logic gate that provide a 20 MHz input to the AD9557. When tested with an input that does not miss any data, the output clock of 20 MHz from AD9557 is jitter-free perfectly phase locked with the input on the oscilloscope. But since it has to work with with real time data that might miss a few pulses, I have been testing it with just one missing pulses (gapped clock) periodically. The input is 19.44 MHz and the output expected is a cleaner phase-locked jitter free 19.44 MHz clock. I think because of the gapped clock the indicators weren't showing Phase and Frequency lock in DPLL as well as APLL lock, therefore I increased the DPLL loop bandwidth to 1000 Hz. At this stage, all the indicators are showing lock and there is slight stability in the output, but it has some jitter as well as its not perfectly locking with the input signal when seen on the oscilloscope, though the output is almost around the expected frequency. My questions are:

 

1. How can I remove the jitter even when the phase and frequency are locked with just one missing pulse (gapped clock) ?

2. If I increase the number of data gaps in the input to AD9557, it doesn't even lock, what do you think I can change to get the output clock less sensitive to gapped clock/missing pulses?

 

The current AD9557 setup is attached. I have only used wizard to change the input/ouput and loop BW values, all the other values are set to reset default. 

  • 0
    •  Analog Employees 
    on Apr 10, 2018 9:37 PM

    Dear ARStrooper,

    First, I apologize for the lag in answering you.

    The AD9557 is used in many gapped clock applications and has performed extremely well.

    > This is continuing from a previous question about gapped clocks on

    > AD9557 (ad9557 and gapped clock? ), which was replied by .

     

    > I am currently working on a clock recovery circuit that should output a phase locked clock. The circuit includes a comparator and a logic gate that provide a 20 MHz input to the AD9557. When tested with an input that does not miss any data, the output clock of 20 MHz from AD9557 is jitter-free perfectly phase locked with the input on the oscilloscope. But since it has to work with with real time data that might miss a few pulses, I have been testing it with just one missing pulses (gapped clock) periodically. The input is 19.44 MHz and the output expected is a cleaner phase-locked jitter free 19.44 MHz clock. I think because of the gapped clock the indicators weren't showing Phase and Frequency lock in DPLL as well as APLL lock, therefore I increased the DPLL loop bandwidth to 1000 Hz. At this stage, all the indicators are showing lock and there is slight stability in the output, but it has some jitter as well as its not perfectly locking with the input signal when seen on the oscilloscope, though the output is almost around the expected frequency. My questions are:

     

     

    > 1. How can I remove the jitter even when the phase and frequency are locked with just one missing pulse(gapped clock) ?

     

    OK. First, keep in mind that the lock detector is informational only. As long as the DPLL is "active," it's actively tracking the input. Also, you don't need to increase the loop BW to regain lock, although it's one way to do it. The problem is that by doing so, you won't filter the input clock jitter as well. Instead, you can increase the phase and frequency lock threshold. In addition, you can also increase the lock detector "fill rate" (and decrease the "drain rate") if increasing the threshold isn't enough to enable the lock detector to declare lock when you desire. These bits are located in Registers 0x71E-0x726.

     

    I'd also recommend that you increase the Inner and Outer Tolerances by writing smaller values to Registers 0x0707 (Input Frequency Inner Tolerance) and 0x070A (Outer Tolerance). Specifically, I recommend writing to R0x0708=0x05,  R0x0705=0x0A, and R0x0706=0x00.

     

    Enable an IRQ on "REFA valid" and ensure that REFA is always valid with the gapped clock. If not, Set R0x0A0D=0x03.

     

    > 2. If I increase the number of data gaps in the input to AD9557, it doesn't even lock, what do you think I can change to get the output clock less sensitive to gapped clock/missing pulses?

     

    See what I wrote above.

     

     

    > The current AD9557 setup is attached. I have only used wizard to change the input/ouput and loop BW values, all the other values are set to reset default. 

     

    OK. Try this changes and let me know if this helps.

     

    -Paul Kern

  • Hi Paul,

    I'm very thankful for your reply. I made the changes as you said and these are the observations.

    Fixing the loop BW to 50Hz, I changed the phase and frequency lock thresholds, as well as fill and drain rate. On making the appropriate changes both the lock detectors definitely show green as well as the input is valid and DPLL is "active". I tried changing the gap frequency and size in input and dpll still shows active. Changes in reference monitor and IRQ keep the input valid and DPLL active.

    Though all of this is working, the clock is still not tracking the input or it is not seen to be locked with the input on the oscilloscope even though it is ACTIVE mode and lock detectors are on. To make the clock stable and close to locking I have to increase the BW to 1000Hz, which does make it stable, but there is a slight jitter. I have tried variation of very high as well as closer to default values of thresholds and fill rate, which do not effect the input tracking that much.

    Since the Active mode means that the input is being tracked, could you think of the reason it is not working. Also, you don't recommend increasing the value of BW, I would be grateful if you could suggest another way.

    I am attaching a sample reg map, that shows the register values. I am inputting a 40 MHz periodic waveform, with gaps of one clock in every 200 usec, or 5 KHz.

  • 0
    •  Analog Employees 
    on Apr 12, 2018 2:17 AM

    Dear Arastrooper,

    Be sure to set R0x070E=0x01 to select high phase margin mode. This allows for additional stability at high loop BWs.

    Be sure to enable IRQs so that you're 100% sure that the DPLL is always active, that the reference input is always valid, and the the DPLL is always locked. My suspicion is that one of those isn't always true, but that it's toggling so quickly, you're not able to detect it.

    -Paul

  • Dear Paul,

    Thanks a lot for all the help and advise. 

    I can see that output locks when REFA is valid and DPLL is active. Although there is still some jitter of about 2-3 ns in the output, which I'm guessing maybe due to the toggling of DPLL or high loop BWs. But I think I can try to decrease the high loop BW and increase the loop threshold values instead.  

    Thank you.

    Arastu

  • Hi ,

    You had previously mentioned that you have checked gapped clock inputs and it worked fine. Could you tell me what frequency was your input and how frequent was your clock gap, also if you were able to get the input and output to be locked. Because the output of the AD9557 still seems to have fluctuations and jitter, which means it is phase locked for a few period of times only. While the input jitter is in the range of 200ps. The output jitter is around 1 ns for edge jitter which I guess is random jitter so its no that big a problem, while the timing jitter is much higher which is happening as I think the phase lock is fluctuating.

    Thanks

    Arastu